MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 147

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
All the timings for the SSI are given for a non-inverted serial clock polarity
(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the
polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing is the
same as that of Tx Data, for example, during the AC97 mode of operation.
Internal Clock Operation
Oversampling Clock Operation
SS11
SS13
SS20
SS21
SS47
SS48
SS49
SS50
SS51
SS1
SS2
SS3
SS4
SS5
SS7
SS9
ID
Table 62. SSI Receiver with Internal Clock Timing Parameters
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
(Rx) CK high to FS (bl) high
(Rx) CK high to FS (bl) low
(Rx) CK high to FS (wl) high
(Rx) CK high to FS (wl) low
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
Oversampling clock period
Oversampling clock high period
Oversampling clock rise time
Oversampling clock low period
Oversampling clock fall time
i.MX31/i.MX31L Advance Information, Rev. 1.4
Parameter
Preliminary
NOTE
NOTE
NOTE
NOTE
15.04
81.4
36.0
36.0
10.0
Min
–
–
–
–
–
–
0
6
–
6
–
Max
15.0
15.0
15.0
15.0
–
–
6
–
6
–
–
–
–
3
–
3
Electrical Characteristics
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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