MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 145

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
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All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)
and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or
the frame sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx
Data (for example, during AC97 mode of operation).
Internal Clock Operation
Synchronous Internal Clock Operation
SS10
SS12
SS14
SS15
SS16
SS17
SS18
SS19
SS42
SS43
SS52
SS1
SS2
SS3
SS4
SS5
SS6
SS8
ID
Table 61. SSI Transmitter with Internal Clock Timing Parameters
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
(Tx) CK high to FS (bl) high
(Tx) CK high to FS (bl) low
(Tx) CK high to FS (wl) high
(Tx) CK high to FS (wl) low
(Tx/Rx) Internal FS rise time
(Tx/Rx) Internal FS fall time
(Tx) CK high to STXD valid from high
impedance
(Tx) CK high to STXD high/low
(Tx) CK high to STXD high impedance
STXD rise/fall time
SRXD setup before (Tx) CK falling
SRXD hold after (Tx) CK falling
Loading
i.MX31/i.MX31L Advance Information, Rev. 1.4
Parameter
Preliminary
81.4
36.0
36.0
10.0
Min
–
–
–
–
–
–
–
–
–
–
–
–
0
–
Max
15.0
15.0
15.0
15.0
15.0
15.0
15.0
25
–
–
6
–
6
6
6
6
–
–
Electrical Characteristics
Unit
ns
ns
ns
ns
ns
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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