MCIMX31L FREESCALE [Freescale Semiconductor, Inc], MCIMX31L Datasheet - Page 17

• Manufacturer Part Number: MCIMX31L
• Description: Multimedia Applications Processors
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

The prescaler converts the incoming crystal reference clock to a 1 Hz signal which is used to increment
the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC
interrupts when the TOD settings reach programmed values. The sampling timer generates
fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on very small
boundaries.
2.3.23
The RTIC is one of the security components in the i.MX31 and i.MX31L. Its purpose is to ensure the
integrity of the peripheral memory contents and assist with boot authentication. The RTIC has the ability
to verify the memory contents during system boot and during run-time execution. If the memory contents
at runtime fail to match the hash signature, an error in the security monitor is triggered.
The RTIC provides SHA-1 message authentication and receives input via the DMA (AMBA-AHB Lite bus
master) interface. It uses segmented data gathering to support non-contiguous data blocks in memory (up
to two segments per block) and works during and with High Assurance Boot (HAB) process. It provides
Secure-scan DFT security and support for up to four independent memory blocks. The RTIC has both a
programmable DMA bus duty cycle timer and its own watchdog timer.
The RTIC operates in two primary modes: One time hash mode and continuous hash mode.
The One time hash mode is used during HAB for code authentication or one time integrity checking during
which it stores the hash result internally and signals the ARM11 using an interrupt. In Continuous hash
mode the RTIC is used continuously to verify integrity of memory contents by checking re-generated hash
against internally stored values and interrupts host only if error occurs.
2.3.24
Security and security services, in an embedded or data processing platform, refer to the i.MX31 and
i.MX31L processor’s ability to provide mandatory and optional information protection services.
Information in this context refers to all embedded data, both program store and data load. Therefore, a
secure platform is intended to protect information/data from unauthorized access in the form of inspection
(read), modification (write) or execution (use). Security assurance refers to the degree of confidence that
security claims are actually met and is therefore associated with the resources available to, and the integrity
of, a given security design.
The SCC is a hardware security component composed of two subblocks, the Secure RAM and the Security
Monitor Overall its primary functionality is associated with establishing a centralized security state
controller and hardware security state with a hardware configured, unalterable security policy. It also
provides an uninterruptedly hardware mechanism to detect and respond to threat detection signals
Freescale Semiconductor
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Minute countdown timer with interrupt
Programmable daily alarm with interrupt
Sampling timer with interrupt
Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts
Operation at 32.768 kHz, 32 kHz, or 38.4 kHz (determined by reference clock crystal)
Run-TIme Integrity Checker (RTIC)
Security Controller Module (SCC)
i.MX31/i.MX31L Advance Information, Rev. 1.4
Preliminary
Functional Description and Application Information
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