AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet
AM8530H
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AM8530H Summary of contents
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... Am8530H/Am85C30 Serial Communications Controller 1992 Technical Manual ...
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Advanced Micro Devices reserves the right to make changes in its products without notice in order to improve design or performance characteristics. This publication neither states nor implies any warranty of any kind, including but not limited to implied warrants ...
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... This manual is intended to provide answers to technical questions about the Am8530H and Am85C30. If you have already used the Am8530H and are familiar with the previous editions of this Technical Manual, you will find that some chapters are virtually unchanged. The Am8030’s functionality, however, has been omitted from this revision since a CMOS Am8030 was not developed ...
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TABLE OF CONTENTS Chapter 1 General Information 1.1 Introduction 1.2 Capabilities 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Descriptions 1.5.1 System Interface Pin Descriptions 1.5.2 Serial Channel Pin Descriptions Chapter 2 System Interface 2.1 Introduction 2.2 Registers . . ...
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Table of Contents Chapter 4 3.9 Block Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD Chapter 5 4.7.2.3 CRC Error . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.2.4 CRC Character Reception 4.7.3 End of Frame ...
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Table of Contents Chapter 6 5.3.1 BRG Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 BRG Enabling/Disabling 5.3.3 ...
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... The 68000 and Am8530H Without Interrupts 7.5.3 The 68000 and Am8530H With Interrupts 7.5.4 The 68000 and Am8530H With Interrupts via a PAL Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CHAPTER 1 General Information 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD 1–2 General Information ...
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... CRC generation and checking, break/ abort generation and detection, and many other protocol-dependent features. Unless otherwise stated, the functional description in this Technical Manual applies to both the NMOS Am8530H and CMOS Am85C30. When the enhancements in the Am85C30 are disabled completely downward compatible with the Am8530H. 1.2 ...
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AMD Asynchronous capabilities: – bits per character – 1, 1-1/ stop bits – Odd or Even Parity – x1, 16, 32 clock modes – Break generation and detection – Parity, Overrun ...
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... General Information 1.3 Figure 1–1 depicts the block diagram of the Am8530H and Figure 1–2 the block diagram of the Am85C30. Data being received enters the receive data pins and follows one of several data paths, depending on the state of the control logic. The contents of the regis- ters and the state of the external control pins establish the internal control logic ...
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... Bus RD RTxCA WR SYNCA W/REQA A/B DTR/REQA CE D/C INT INTACK IEI IEO TRxCB RTxCB SYNCB W/REQB DTR/REQB Am85C30/ Am8530H SCC GND +5 V PCLK Figure 1–3. SCC Pin Functions General Information TxDA Serial Data RxDA Channel Clocks Channel Controls for Modem, RTSA DMA, or CTSA Other ...
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... General Information INTACK W/REQA INT 5 IEO 6 IEI 7 Am8530H 8 INTACK Am85C30 REQA 11 SYNCA 12 RTxCA 13 RxDA 14 TRxCA 15 TxDA DTR / REQA 16 17 RTSA 18 CTSA DCDA 19 20 PCLK IEO IEI Am85C30 ...
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... WR — Write (input, active Low) When the SCC is selected, this signal indicates a Write operation. On the NMOS Am8530H data must be valid prior to the rising edge of write strobe. The Am85C30 does not share this requirement. The coincidence of RD and WR is interpreted as a Reset. ...
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General Information 1.5.2 CTSA, CTSB — Clear to Send (inputs, active Low) If the Auto Enable bit in WR3 (D5) is set, a Low on these inputs enables the respective transmitter; otherwise they may be used as general-purpose inputs. Both ...
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AMD these outputs are active each time a sync character is recognized (regardless of charac- ter boundaries). In SDLC mode, these pins act as outputs and are valid on receipt of a flag. TRxCA, TRxCB — Transmit/Receive Clocks (inputs or ...
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CHAPTER 2 System Interface 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD 2–2 System Interface ...
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CHAPTER 2 System Interface 2.1 INTRODUCTION The SCC internal structure provides all the interrupt and control logic necessary to inter- face with non-multiplexed buses. Interface logic is also provided to monitor modem or peripheral control inputs or outputs. All of ...
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AMD Read Register Functions RR0 RR1 RR2 RR3 *RR6 *RR7 RR8 RR10 RR12 RR13 RR15 * Available only when Am85C30 is programmed in enhanced mode. Write Register Functions WR0 WR1 WR2 WR3 WR4 WR5 WR6 WR7 **WR7 WR8 WR9 WR10 ...
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... Am8530H/Am85C30, and any intervening transactions are ignored. This recovery time is four PCLK cycles, measured from the falling edge for a read or write cycle of any SCC register on the Am8530H-step and 3 or 3.5 PCLK cycles for the Am85C30. Note that RD and the WR inputs are ignored until CE is activated. The falling edge of RD and WR can be substituted for the falling edge vice versa for calculating proper pulse width for low ...
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AMD 2.4 REGISTER ACCESS The registers in the SCC are accessed in a two-step process, using a Register Pointer to perform the addressing. To access a particular register, the pointer bits must be set by writing to WR0. The pointer ...
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System Interface A/B, D/C INTACK PCLK D – INTACK IEI IEO INT 2.5 SDLC/HDLC enhancements on the Am85C30 are enabled or disabled via bits D2 and D0 in WR15. ...
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AMD A A/B With the Point High command: [D5–3 (WR0) = 001 ...
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System Interface WR15 bit D2 10x19-bit FIFO Enabled Enhance Enabled Bit D0 of WR15 determines whether or not other enhancements pertinent only to SDLC/ HDLC Mode operation are available for programming via WR7 as shown ...
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AMD A With the Point High command 2–10 ...
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System Interface A With the Point High command ...
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AMD If both bits D0 and D2 of WR15 are set to ‘1’ then the Am85C30 register map is as shown in Table 2–6. A ...
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System Interface hardware reset to ensure that the FIFO is completely flushed before the new data can be received reliably. The SCC has three software resets encoded into command bits in WR9. There are two channel resets, which affect only ...
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CHAPTER 3 I/O Programming Functional Description 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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I/O Programming Functional Description 3–2 AMD ...
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CHAPTER 3 I/O Programming Functional Description 3.1 INTRODUCTION The SCC can work under one of the following three modes of I/O operations: Polling, Interrupts, and Block transfer. All three modes involve register manipulation during initiali- zation and data transfer. Regardless ...
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AMD INT on 1st Rx Char. or Special Condition INT on All Rx Char. or Special Condition Rx Int on Special Condition only Parity Transmit Buffer Empty Zero Count DCD SYNC/HUNT CTS Tx Underrun/EOM Break/Abort 3.4 INTERRUPT CONTROL In addition ...
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I/O Programming Functional Description D7 W/DMA REQ Enable 3.4.2 The Interrupt Pending (IP) bit for a given source of interrupt may be set by the presence of an interrupt condition in the SCC and is reset directly by the processor, ...
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AMD 3.5 INTERRUPT OPERATIONS Interrupts from the SCC may be acknowledged with a vector, acknowledged without a vector, or not acknowledged at all. WR2 is used to hold the interrupt vector returned dur- ing an interrupt acknowledge cycle. This vector ...
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I/O Programming Functional Description 5 V IEI IP RECEIVER CHANNEL A IEI Each SCC on the daisy chain uses PCLK to latch the state of the Interrupt Acknowledge signal, INTACK Low INTACK is latched, then the present cycle ...
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AMD The interrupt protocol is diagrammed in Figure 3–5. In the quiescent state (i.e. no inter- rupts pending or under service) each SCC on the daisy chain passes its IEI input through to its IEO output. An interrupt source that ...
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I/O Programming Functional Description Start Interrupt No Condition Exits ? Yes Specific No Interrupt Enable (IEx = 1) ? Yes Interrupt Pending Set ( Master No Interrupt Enables (MIE = 1) ? Yes IS Peripheral No Enable Pin ...
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AMD 3.5.4 Interrupt With Acknowledge Without Vector If the No Vector bit in WR9 (D1) is set to ‘1’, the SCC will not place the vector on the data bus during the Interrupt Acknowledge cycle. An external interrupt controller must ...
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I/O Programming Functional Description The SCC recognizes several Special Conditions during data reception. A Receiver Over- run, where a character in the Data FIFO is overwritten Special Condition Framing Error in Asynchronous mode, or the ...
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AMD the status and unlock the FIFO by issuing an Error Reset command. DMA transfer of the receive characters will then resume. If Receive Interrupts on Special Condition Only is enabled and a Special Condition occurs then modified ...
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I/O Programming Functional Description 3.8 The External/Status Interrupts are globally enabled via WR1 and may be individually en- abled via WR15 as shown below. The External/Status interrupt sources are: 1) Zero Count, 2) DCD, 3) SYNC/HUNT, 4) CTS ...
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AMD In External Sync Mode, the SYNC/HUNT status bit Asynchronous mode, reports the state of the SYNC pin. If there are no other External/Status interrupts pending, then any transition on the SYNC pin will cause the latches to ...
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I/O Programming Functional Description 3.8.4 The Tx Underrun/EOM status bit is used in SDLC and Synchronous modes of operation to control the transmission of CRC characters. This bit is set to ‘1’ when the Transmit Buffer and Transmit Shift Register ...
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AMD D7 D7 Wait/ DMA REQ Enable Each channel in the SCC has two pins, DTR/REQ and W/REQ, which may be used to control the block transfer of data. Both pins in each channel may be programmed to act as ...
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I/O Programming Functional Description In this mode, the W/REQ pin carries the Wait signal, and is open-drain when inactive and Low when active. When the processor attempts to read data from the Receive Data FIFO and it is empty, the ...
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AMD In this mode the W/REQ pin carries the DMA Request signal, which is active Low. When this mode is selected, but not yet enabled, the W/REQ pin is driven High. When the en- able bit is set, W/REQ will ...
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I/O Programming Functional Description 3.3.9.3 On the NMOS SCC, the DMA Request function on DTR/REQ differs from the one on W/REQ in that it does not go High immediately in response to the access which writes to WR8. This is ...
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AMD DMA Request on Receive (Using W/REQ) 3.3.9.4 The DMA Request on Receive function using the W/REQ pin is selected by programming WR1 as shown below. In this mode, the W/REQ pin carries the DMA Request signal, which is active ...
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I/O Programming Functional Description RTxC 1 PCLK WAIT WR D – PCLK REQ 5...8 Figure 3–10. DTR/REQ Activation Receive Data Figure 3–11. DTR/REQ Deactivation AMD SYNC Modes ASYNC Modes 13 ...
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CHAPTER 4 Data Communication Modes Functional Description 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD 4.8 Transmitter Operation 4.8.1 Transmitter Initialization 4.8.2 Mark/Flag Idle Generation 4.8.3 Auto Flag Mode 4.8.4 Abort Generation 4.8.5 Auto Transmit CRC Generator Preset 4.8.6 CRC Transmission 4.8.7 Auto Tx Underrun/EOM Latch Reset 4.8.8 Transmitter Disabling 4.8.9 NRZI Mode Transmitter ...
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CHAPTER 4 Data Communication Modes Functional Description 4.1 INTRODUCTION The SCC provides two independent full-duplex channels programmable for use in any common asynchronous or synchronous data communication protocol. This includes: Asynchronous, Synchronous MONOSYNC (8-bit sync character), Synchronous BISYNC (16-bit sync ...
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AMD 4.2.2 Synchronous Transmission Synchronous transmission requires that clocking information be transmitted along with the data, either by a method of encoding data that contains clocking information modem that encodes clock information in the modulation process. In ...
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Data Communication Modes Functional Description and provides the mechanism by which character synchronization is established at a re- ceiver. Since data between flags may contain the flag pattern, the sequence of six con- secutive one bits is prevented from occurring ...
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AMD 4.4 RECEIVER OVERVIEW The receiver performs all the functions necessary to convert serial data back to parallel for the processor. The receiver block diagram is shown in Figure 4–5. Serial data on the RxD pin is sampled on the ...
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Data Communication Modes Functional Description ter with the Special Condition is read from the Data FIFO. Because under these condi- tions the FIFO is locked, and prevented from being updated, the status pertinent to the character read will be valid ...
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AMD The character length may be changed at any time before the new number of bits have been assembled by the receiver. Care should be exercised, however, as unexpected re- sults may occur if not properly timed. A representative example ...
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Data Communication Modes Functional Description The Parity Error bit in the Receive Error FIFO may be programmed to cause a Special Condition interrupt by setting bit D2 of WR1 to ‘1’. If this interrupt mode is programmed, and a Parity ...
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AMD Internal Data Bus WR7 Sync Register 20-Bit Transmit Zero Insert (5 Bits) CRC Generator The serial data stream sent by the transmitter for the six bits/character with ...
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Data Communication Modes Functional Description The character length may be changed at any time, but the desired length must be se- lected before the character in the transmit buffer is transferred to the the Transmit Shift Register. The easiest way ...
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AMD Tx Underrun/EOM RTS bit D1 WR5 RTS pin (active low) 4.6 ASYNCHRONOUS MODE OPERATION 4.6.1 Receiver Operation In Asynchronous mode, the receiver establishes bit and character synchronization by sensing the High-to-Low transition of the Start-bit for each character. When ...
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Data Communication Modes Functional Description 4.6.1.3 A break condition is recognized when a null character (all ‘0’s) plus a Framing Error is detected by the receiver. Upon recognizing this sequence, the BREAK/ABORT status bit in RR0 will be set and ...
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AMD 4.7 SDLC MODE OPERATION 4.7.1 Receiver Operation Receiver operation in SDLC mode begins in a Hunt mode where the communications line is monitored for a synchronizing pattern on a bit-by-bit basis. The receiver may be placed in Hunt mode ...
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Data Communication Modes Functional Description back SDLC frames by minimizing frame overruns due to CPU latencies in responding to interrupts. The block diagram of the 10x19-bit FIFO is shown in Figure 4–12. 4.7.1.3.1 This Frame Status FIFO is enabled through ...
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AMD SCC Status Reg RR1 (Existing) Residue Bits(3) Overrun CRC Error 6-Bit MUX 2 Bits 6 Bits RR1 Interface to SCC In SDLC Mode the Following Definitions Apply • All Sent Bypasses MUX and Equals Contents of SCC Status Register ...
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Data Communication Modes Functional Description Since not all status bits of RR1 are stored in the Frame Status FIFO, the All Sent, Parity, and EOF bits bypass the FIFO and are stored in the 8-bit Status FIFO. The status bits ...
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AMD Internal Byte Strobe Increments Counter Don't Load Counter On 1st Flag Reset Byte Counter Here 4.7.1.3.5 Am85C30 Frame Status FIFO Operation Clarification In an effort to make the 10x19 Frame Status FIFO (FSF) ...
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Data Communication Modes Functional Description i. The Status x11 will be reported when the first special conditions is received. ii. As more data is received, the status will switch to x10 to reflect that a Receiver interrupt has been received, ...
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AMD The address comparison will be across all eight bits of WR6 when the Sync Character Load Inhibit bit (D1 in WR3) is set to ‘0’. This comparison may be modified so that only the four most significant bits of ...
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Data Communication Modes Functional Description status bit may be able to provide the indication that an abort pattern was received, since an abort condition places the receiver in Hunt mode. 4.7.1.6 Since the information field of an SDLC/HDLC frame can ...
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AMD Because the bit pattern used by the receiver for CRC error checking is based on an in- dustry standard polynomial, only the CRC-CCITT polynomial (X used in SDLC mode. The CRC transmission and CRC-CCITT polynomial are enabled by programming ...
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Data Communication Modes Functional Description Residue Code ...
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AMD ...
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Data Communication Modes Functional Description ...
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AMD Residue Code Residue Code Residue Code 0 1 ...
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Data Communication Modes Functional Description 4.8 In SDLC Modes, the transmitter automatically envelopes the data written to the Transmit Buffer Register (WR8) with the flag character in WR7. Because the SCC transfers the flag character eight bits at a time, ...
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AMD (so the Reset Tx CRC Generator command is also not necessary), and the Tx Underrun/ EOM latch will be reset automatically on every new frame sent. This ensures that an opening flag and proper CRC generation and transmission will ...
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Data Communication Modes Functional Description The Tx Underrun/EOM status bit in RR0 will be set to ‘1’ by the SCC to indicate that an underrun has occurred, and that either the CRC, or abort character, has been loaded into the ...
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AMD nization at the receiver may take longer because the first transition seen on the TxD pin may not coincide with a bit boundary. Note that in order for this to function properly, bits D3 and D2 of WR10 must ...
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Data Communication Modes Functional Description 4.9.1.1 SDLC Loop mode is similar to SDLC mode except that two additional control bits are used. They are the Loop mode bit (D1) and the Go Active on Poll bit (D4) in WR10. In ...
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AMD nects TxD from RxD. To ensure proper loop operation after the SCC goes off the loop, and until the external relays take the SCC completely out of the loop, the SCC should be programmed for mark idle instead of ...
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Data Communication Modes Functional Description via bit D4 in WR3. The Enter Hunt Mode bit in WR3 is a command so writing a ‘0’ has no effect. In Synchronous modes, once character synchronization has been established, Hunt mode ...
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AMD RTxC PCLK SYNC SYNC SYN 4.10.1.2 SYNC Character Length In Synchronous modes, the sync character length that is used during transmit and receive operations is programmable via bit D0 of WR10. If this bit is set to ‘0’ in ...
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Data Communication Modes Functional Description cient transitions to allow self-clocking devices to remain in sync. Under these conditions the equipment in use today will send sync characters in order to maintain character phase. In this case the receiver may want ...
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AMD 4.10.1.5 CRC Polynomial Selection Either of two CRC polynomials may be used in Synchronous modes. The polynomial that will be used by both the transmitter and receiver is selected by bit D2 in WR5. If this bit is set ...
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Data Communication Modes Functional Description in the Receive Shift register. Now F is transferred to the receive data FIFO and CRC is enabled. During the next eight-bit-times the processor reads F and leaves the CRC en- abled. The processor is ...
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AMD Receive Data Figure 4–24. Receive CRC Data Path for Synchronous Mode 4.10.2.2.1 Tx CRC Initialization The initial state of the transmit and receive CRC generators is controlled by bit D7 of WR10. When this bit is set to ‘1’, ...
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Data Communication Modes Functional Description The Tx Underrun/EOM status bit in RR0 will be set to ‘1’ to indicate that an underrun has occurred, and that the CRC, or sync characters, have been loaded into the Transmit Shift Register for ...
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AMD Beyond this point the receiver and transmitter are again completely independent, except that the character boundaries are now aligned. This is shown in Figure 4–25. There are several restrictions on the use of this feature. First, it will work ...
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Data Communication Modes Functional Description The SYNC input falling edge (synchronized through some internal circuitry) essentially removes the Receiver from “Hunt Mode” in which it is waiting for synchronization before accepting Receive Data. Upon exiting “Hunt Mode”, the Receiver will ...
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AMD RTxC RxD SYNC SYNC 4–42 Data Communication Modes Functional Description SYNC DATA LAST–1 LAST 0 Figure 4–27. External SYNC Receiver Synchronization DATA DATA 1 2 ...
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CHAPTER 5 Support Circuitry Programming 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD 5–2 Support Circuitry Programming ...
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CHAPTER 5 Support Circuitry Programming 5.1 INTRODUCTION The SCC incorporates additional logic on-chip which dramatically reduces the need for external hardware. This includes clocking options, baud rate generators, clock recovery logic, on-chip oscillators, and internal loopback modes. This chapter discusses ...
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AMD 5.2.2 Receive Clock Source The source of the receive clock is controlled by bits D6 and D5 of WR11. The receive clock may be programmed to ...
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Support Circuitry Programming Figure 5–1 shows a simplified schematic diagram of the circuitry used in the clock multi- plexing. It shows the inputs to the multiplexer section as well as the various signal inver- sions that occur in the paths ...
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AMD 5.3 BAUD RATE GENERATOR (BRG) Each channel in the SCC contains a programmable BRG. Each generator consists of two 8-bit, time-constant registers forming a 16-bit time constant, a 16-bit down counter, and a flip-flop on the output that makes ...
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Support Circuitry Programming If neither the transmit clock nor the receive clock is programmed to come from the TRxC pin, the output of the BRG may be made available for external use on the TRxC pin. Figure 5–2 shows a ...
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AMD 5.3.1 BRG Clock Source The clock source for the BRG is selected by bit D1 of WR14. When this bit is set to ‘0’, the BRG uses the signal on the TRxC pin as its clock, independent of whether ...
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Support Circuitry Programming 5.3.3 Initializing the BRG is done in four steps. First, the time-constant is determined and loaded into WR12 and WR13. Next, the processor must select the clock source for the BRG by writing to bit D1 of ...
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AMD 5.4.3 FM1 (Biphase Mark) In FM1 encoding, also known as biphase mark, a transition is present on every bit cell boundary, and an additional transition may be present in the middle of the bit cell. In FM1, a ‘0’ ...
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Support Circuitry Programming 5.5.1 The clock for the DPLL is selected by two of the commands in WR14. One command se- lects the output of the BRG as the clock source, and the other command selects the RTxC pin as ...
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AMD Bit Cell Count Correction No Change DPLL Out However, if the transition marking a bit cell boundary occurs between the middle of count 16 and count 31 the DPLL is sampling the data too early ...
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Support Circuitry Programming However, if the transition marking a bit cell boundary occurs between the middle of count 16 and the middle of count 19 the DPLL is sampling the data too early in the bit cell. In response to ...
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AMD With all three of these data encoding methods there will be at least one transition in every bit cell, and in FM mode the DPLL is designed to expect this transition. In particular transition occurs between the ...
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Support Circuitry Programming 5.5.4 Initialization of the DPLL may be done at any time during the initialization sequence, but should probably be done after the clock modes have been selected in WR11, and before the receiver and transmitter are enabled. ...
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AMD 5.6.1 Local Loopback Local loopback is selected when bit D4 of WR14 is set to ‘1’. In this mode the output of the transmitter is internally connected to the input of the receiver. At the same time the TxD ...
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CHAPTER 6 Register Description 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD 6–2 Register Description ...
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CHAPTER 6 Register Description 6.1 INTRODUCTION The following sections describe the SCC registers. Each register is detailed in terms of bit configuration, the active states (See Table 6–1) of each bit, their definitions, their func- tions, and their effects upon ...
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AMD Read Register Functions RR0 RR1 RR2 RR3 *RR6 *RR7 RR8 RR10 RR12 RR13 RR15 * Available only when Am85C30 is programmed in enhanced mode. Write Register Functions WR0 WR1 WR2 WR3 WR4 WR5 WR6 WR7 **WR7 WR8 WR9 WR10 ...
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Register Description 6.2 The SCC write register set for each channel includes ten control registers, two sync char- acter registers, two baud rate time constant registers, a transmit buffer, and a master in- terrupt register. The following sections describe in ...
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AMD Bits D7 and D6: CRC Reset Codes 0 and 1 Null code (00). This command has no effect on the SCC and is used when a write to WR0 is necessary for some reason other than a CRC Reset ...
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Register Description buffer or until CRC has been completely sent. This command is necessary to prevent the transmitter from requesting an interrupt when the transmit buffer becomes empty again, (with Transmit Interrupt Enabled) on the last data character transmitted. Error ...
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AMD Bits 4 and 3: Receive Interrupt Modes These two bits specify the various character-available conditions that may cause interrupt requests. Receive Interrupts Disabled (00). This mode prevents the receiver from requesting an interrupt and is normally used in a ...
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Register Description Receive Interrupt on Special Condition (11). This mode allows the receiver to interrupt only on characters with a special receive condition. When an interrupt occurs, the data containing the error are held in the receive FIFO until an ...
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AMD 6.2.4 Write Register 3 (Receive Parameters and Control) This register contains the control bits and parameters for the receiver logic as illustrated in Figure 6–4. This register is readable by executing a Read to RR9 when D0 of WR15 ...
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Register Description Bit 2: Address Search Mode (SDLC) Setting this bit in SDLC mode causes messages with addresses not matching the ad- dress programmed in WR6 to be rejected. No receiver interrupts can occur in this mode unless there is ...
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AMD Bits 7 and 6: Clock Rate 1 And 0 These bits specify the multiplier between the clock and data rates. In synchronous modes, the 1X mode is forced internally and these bits are ignored unless External Sync mode has ...
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Register Description The transmitter uses the character stored in WR6 as a time fill. The sync character can be either six or eight bits, depending on the state of the 6-bit/8-bit Sync bit in WR10. If the Sync Character Load ...
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AMD Bit 7: Data Terminal Ready This is the control bit for the DTR/REQ pin while the pin is in the DTR mode (selected in WR14). When set, DTR is Low; when reset, DTR is High. This bit is ignored ...
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Register Description Bit 3: Transmit Enable Data is not transmitted until this bit is set, and the TxD output sends continuous ‘1’s un- less Auto Echo mode or SDLC Loop mode is selected. If this bit is reset after transmis- ...
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AMD SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC ADR ADR ADR ADR 7 6 ...
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... Register Description 6.2.8 In the Nmos Am8530H, the use of this register differs depending on the mode the SCC is programmed in. In Monosync mode, WR7 is programmed with the receive sync charac- ter; in BISYNC programmed with the second byte (the last 8 bits) of the 16-bit sync character. In SDLC modes, WR7 is programmed with the flag character (01111110). ...
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AMD Bit 4: DTR / REQ Timing Mode This bit controls the timing of the DTR/REQ pin. If this bit is set to ‘1’, the deactivation tim- ing of the DTR/REQ pin is made identical to the WAIT/REQ pin. Bit ...
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Register Description Bits 7 and 6: Reset Command Bits Together, these bits select one of the reset commands for the SCC. Setting either of these bits to ‘1’ disables both the receiver and the transmitter in the corresponding chan- nel, ...
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AMD Bit 2: Disable Lower Chain The Disable Lower Chain can be used by the CPU to control the interrupt daisy chain. Setting this bit to ‘1’ forces the IEO pin Low, preventing lower-priority devices on the daisy chain from ...
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Register Description Transmit Clock Data NRZ NRZI FM1 FM0 Receive Clock Data NRZ NRZI FM1 FM0 Bit 7: CRC Presets ‘1’ or ‘0’ This bit specifies the initialized condition of the receive CRC checker and the transmit CRC generator. If ...
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AMD Bit 4: Go Active On Poll When Loop mode is first selected during SDLC operation, the SCC connects RxD to TxD with only gate delays in the path. The SCC does not go on-loop and insert the 1-bit delay ...
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Register Description Bit 2: Abort/ Flag On Underrun This bit affects only SDLC operation and is used to control how the SCC responds to a transmit underrun condition. If this bit is set to ‘1’ and a transmit underrun occurs, ...
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AMD Bit 7: RTxC—XTAL/ NO XTAL This bit controls the type of input signal the SCC expects to see on the RTxC pin. If this bit is set to ‘0’, the SCC expects a TTL-compatible signal as an input to ...
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Register Description Bits 4 and 3: Transmit Clock 1 and 0 These bits determine the source of the transmit clock as shown in Table 6–7. They do not interfere with any of the modes of operation of the SCC but ...
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AMD 6.2.13 Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) WR12 contains the lower byte of the time constant for the baud rate generator. The time constant can be changed at any time, but the new value ...
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Register Description 6.2.15 WR14 contains some miscellaneous control bits. Bit positions for WR14 are shown in Fig- ure 6–16. Bits 7 and 5: Digital Phase-Locked Loop Command Bits These three bits encode the eight commands for the Digital Phase-Locked Loop. ...
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AMD Enter Search Mode (001). Issuing this command causes the DPLL to enter the Search mode, where the DPLL searches for a locking edge in the incoming data stream. The ac- tion taken by the DPLL upon receipt of this ...
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Register Description RxD input. Transmitted data are never seen inside or outside the SCC in this mode, and CTS is ignored as a transmit enable. This bit is reset by a channel or hardware reset. Bit 2: DTR/Transmit DMA Request ...
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AMD Bit 7: Break/Abort IE If this bit is set to ‘1’, a change in the Break/Abort status of the receiver causes an Exter- nal/Status interrupt. This bit is set by a channel or hardware reset. Bit 6: Tx Underrun/EOM ...
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Register Description Bit 7: Break/Abort In the Asynchronous mode, this bit is set when a Break sequence (null character plus framing error) is detected in the receive data stream. This bit is reset when the sequence is terminated, leaving a ...
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AMD The XTAL oscillator should not be selected in External Sync mode. In Asynchronous mode, the operation of this bit is identical to that of the CTS status bit, except that this bit reports the state of the SYNC pin. ...
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Register Description the Low-to-High transition on ZC. The interrupt service routing should check the other External/Status conditions for changes. If none changed, ZC was the source. In polled applications, check the IP bit in RR3A for a status change and ...
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AMD have been read out by a DMA controller independently from the CPU but the CRC status is still available in the Frame Status FIFO. Bit 5: Receiver Overrun Error This bit indicates that the receive FIFO has overflowed. Only ...
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Register Description Bit 0: All Sent In Asynchronous mode, this bit is set when all characters have completely cleared the transmitter. Most modems contain additional delays in the data path, which require the modem control signals remain active until after ...
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AMD 6.3.5 Read Register 6 When the SCC is programmed for SDLC operation and bit D2 of WR15 is set to ‘1’, RR6 contains the LSB of a frame byte count stored in the 10x19-bit ...
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Register Description 6.3.7 RR8 is the Receive Data register. 6.3.8 RR10 contains some miscellaneous status bits. Unused bits are always ‘0’. Bit positions for RR10 are shown in Figure 6–24. Bit 7: One Clock Missing While operating in the FM ...
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AMD 6.3.9 Read Register 12 RR12 returns the value stored in WR12, the lower byte of the time constant for the baud rate generator. Figure 6–25 shows the bit positions for RR12. 6.3.10 Read Register 13 RR13 returns the value ...
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Register Description 6.3.11 RR15 reflects the value stored in WR15, the External/Status IE bits. The unused bit is always returned as ‘0’ unless the corresponding bits in WR15 have been set to ‘1’. In the NMOS SCC, bits D Read ...
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... The 68000 and Am8530H Without Interrupts 7.5.3 The 68000 and Am8530H With Interrupts 7.5.4 The 68000 and Am8530H With Interrupts via a PAL Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD 7–2 SCC Application Notes ...
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... CHAPTER 7 SCC Application Notes 7.1 Am8530H INITIALIZATION 7.1.1 Introduction This application note describes the software initialization procedure for the Am8530 Serial Communications Controller (SCC). Table 7–1 provides a worksheet that can be used as an aid when initializing the SCC. Since all SCC operation modes are initialized in a similar manner, the worksheet can be used to tailor the SCC device to the user’ ...
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AMD Bits D4–D0 are Mode bits that can be enabled or disabled either by being set to ‘1’ or re- set to ‘0’. Each Mode bit affects only one function. For example, Bit D1 is the No Vector mode bit; ...
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SCC Application Notes Register Modes Enables Interrupt Table 7–1. SCC Initialization Worksheet HEX WR9 WR0 WR4 0 WR1 WR2 WR3 WR5 WR6 WR7 0 0 WR9 WR10 WR11 WR12 WR13 WR14 ...
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AMD 1 = Set to one 0 = Reset to zero prog. 7.1.1.3 Initialization Table Generation Table 7–1 as shown previously worksheet for the initialization of the SCC. All the bits that must be programmed as either a ...
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SCC Application Notes 7.2 7.2.1 This section describes the use of the SCC in polled Asynchronous mode. The device can be set with bits per character rates. In this particular example, 8 bits per character, ...
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AMD 7.2.2 SCC Interface Figure 7–2 shows the SCC to CPU interface required for this application. The 8-bit data bus and control lines all come from the user’s CPU. The Am8530 control lines are RD, WR, A/B, D/C and CE. ...
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SCC Application Notes 7.2.3.1 WR9 resets the SCC to a known state by writing a C0 hex. The Force Hardware Reset command is identical to a hardware reset. It will reset both channels. WR4 selects the Asynchronous mode, ...
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AMD WR14 selects the baud-rate generator as the RTxC pin, baud-rate generator disabled, and internal loopback. The baud-rate generator uses the RTxC pin as the clock source and is not enabled at this time because the SCC initialization is not ...
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SCC Application Notes 7.3 7.3.1 This section describes the use of the SCC for interrupt-driven Asynchronous mode. As with the example in the previous chapter, the SCC is set with 8 bits per character, 2 stop bits, at 9600 baud ...
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AMD Table 7–6. SCC Initialization Order for Interrupt Driven Asynchronous Mode Register WR9 WR4 WR2 WR3 WR5 WR9 WR10 WR11 WR12 WR13 WR14 Enables WR14 WR3 WR5 Enable Interrupts WR1 WR9 7.3.3.1 SCC Operating Modes Programming WR9 resets SCC to ...
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SCC Application Notes WR12 & WR13 select the baud-rate generator time constant. The time constant is deter- mined by the equation: In this example, the clock frequency is 2.4576 MHz, the baud rate is 9600, and the clock mode is ...
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AMD 7.3.4 Interrupt Routine When the SCC has been initialized and enabled ready for communication. The trans- mitter buffer and the receive FIFO are both empty. An interrupt will not be generated until the software writes the first ...
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... Most common systems demultiplex address and data. The Am8530H is compatible with these systems. Interface between the 8086 and the Am8530H peripheral device shows how to take ad- vantage of its interrupt structure as shown in Figure 7–6. INTACK is generated by the 8086’s first INTA pulse. This allows about 800 nsec for the interrupt daisy chain to settle. ...
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... – 74LS04 74LS04 PRE Reset D Q 74LS74 Q CP 74LS04 D Q 74LS74 Q CP CLR Figure 7–6. 8086—SCC Interface SCC Application Notes is the same, the few extra bits 7 CS D/C Am8530H INT INTACK 74LS02 74LS02 RD WR ...
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SCC Application Notes T 1 186 INTA INTA 1 INTA 2 RESET INTA RESET INTA = INTACK 125 125 = 1000 200 = 1200 ...
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AMD 7.5.1.2 Initialization Routines The sample assembly initialization routine, Figure 7-9 takes into account the READ/ WRITE recovery time and has been tested MHz system. The interrupt service routines for Channel B are for testing only and ...
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SCC Application Notes /********************************************************************* /* /* /************************************************************************** #include #define #define #define #define #define main () { unsigned char table[tablesize]; unsigned long *ptspa, *ptdpa; unsigned char value; int i; /* data table for initialization */ table[0]=0x9; table[l]=0xC0; table[2]=0x3; table[3]=0x41; table[4]=0x4; table[5]=0x4C; ...
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... Enable signal at one-tenth of the processor clock fre- quency. There are a number of AMD proprietary third generation peripherals that can be interfaced to the 68000 CPU, to improve system performance. This chapter deals mainly with the interfacing of the 68000 and the Am8530H. 7–20 A ...
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... Implementation of an interface without interrupt is straightforward. INTACK must be tied High when not in use and the shift register provides a means for inserting Wait States. Figure 7–11 shows the interface between the 68000 and the Am8530H. The Am8530H SCC. It supports all advanced protocols and has a number of user programmable fea- tures that provide design flexibility ...
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... DTACK signal to the CPU. This allows RD and WR to obtain the required 400 ns width the Am8530H while the remaining address lines are connected to the Am29809 ad- dress comparator. The Am29809 Comparator and the Am29806 Comparator/Decoder provides high-speed address selection as well as an open collector acknowledge driver. This allows memories and peripherals to be conveniently wire-ORed to the processor’ ...
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... The 74LS148 and the two 74LS138s assume there are other interrupting devices which are not compatible with the interrupt daisy chain of the Am8530H. The 74LS148 and one of the 74LS138 can be eliminated if this is not the case. The first 74LS138 acts as a status decoder gated with AS to de-glitch the outputs. ...
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... ACK V CC OSC CLOCK LDS AmPAL RW 16R4 AS 68K85XX Figure 7–14. 68000 to Am8530 Connection using a PAL SCC Application Notes G Am8530H ANYE V CC INT ACK INTA INTA D • • ...
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... The timing during register programming is not shown. The PAL device allows selection of one or two Wait States by making W0 High or Low respectively. The table below shows the appropriate number of Wait Sates as a function of CPU speed. Figure 7–15. PAL Timing The 68000 and Am8530H with Interrupts via a PAL Device CPU Speed 4 MHz ...
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... SINCE THE FLIP–FLOP OUTPUTS ARE NOT USED DIRECTLY. EDGE DELAYED IN ORDER TO GUARANTEE THE SETUP TIME REQUIREMENTS. 7.6 Am7960 AND Am8530H APPLICATION 7.6.1 Distributed Data Processing Overview The changing data-processing environment has created attractive opportunities for dis- tributed processing, encouraging both users and vendors to support the concept. Distrib- uted processing provides either functional or geographical dispersion while integrating the dispersed parts into a coherent system ...
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SCC Application Notes functionally distributed computers. Lengthy delays are often encountered in a centralized system due to overloaded CPUs and slow communication lines. f. Resource Sharing— Remote sites in a distributed system can use each other’s facilities such as sharing ...
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... Bus architectures (full-duplex and half-duplex) Token Passing Ring (SDLC Loop Mode) STAR Configurations (similar to SLAN) The power and flexibility of the Am8530H, along with the Am7960’s CSMA-CA access scheme. Manchester coding of data and output slew rate control enable the system de- signer to deliver an inexpensive 1 Mb/s LAN. ...
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... The RxC rising edge to RxD valid time on the Am7960 varies from – +20ns. The Am8530H clocks in data on the rising edge of RxC and requires a set- least 0 ns from RxD to the rising edge of RxC. This set-up time will not be met if the same RxC edge that clocks out data from the Am7960 is used to clock in data to the Am8530H ...
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... AMD V CC 2947 D0- A1-A0 B1-B0 11 I/R CD INT DRQ1 AD0 IOR IOW PLCK AD1 DACK1 ACM Figure 7–18. 7960-Am8530H Hardware Interface Diagram 7– 2.0 RTSA D0-D7 12- TxDA 1K 14 TRxCA 5 INT 18 CTSA Am8530H 10 W/REQA 19 DCDA 32 12 RTxCA D/C 13 RxDA 36 RD 22µ INTACK ...
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... SCC Application Notes CPU DEVICE 2 DEVICE 3 Figure 7–20. Star Network and Token Passing Ring (SDLC Loop Mode) DEVICE 2 Am7960 CDT Am8530H SCC Am9517 DMA MEMORY DEVICE 1 Figure 7–19. Bus Architecture DEVICE 1 CENTRAL CONTROLLER DEVICE 4 1 MBPS DATA LINK AMD 7511 COAX ...
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... STAR configurations, or Token Passing Ring, or Loop configurations (shown in Figure 7–20). In addition to this 1Mb/s LAN using the Am7960, channel B of the Am8530H is configured to operate a low speed RS-423/RS-232C asynchronous link. The Am26LS29 driver and the Am26LS32 receiver were added, as shown in Figure 7–18, to provide proper signal conditioning for the cable ...
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... Hence, before transmission, the user can select whether the data transfer is over a 1 Mb/ s-network to similar PCs, or over a slower link to a printer. SUMMARY The Am8530H can be software-manipulated to perform at a higher degree of sophistica- tion without any change in hardware connections. Changing or adding to the software does not affect the Am7960 operation. Hence, the Am7960 provides an easy upgrade (high-speed, greater distance, common-mode isola- tion) for most modern modem circuits that use RS-422 drivers and receivers ...
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AMD SOFTWARE ROUTINES Software to Transmit Data at 1 Mb/s Using DMA #include “stdio.h” #define arraysize 40 #define port 0x0382 #define aport 0x0380 #define aportd 0x0381 #define arraysiz 18 unsigned char *ptr; unsigned int segread(); struct(int scs, sss, sds, ses; ...
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SCC Application Notes /*THIS ROUTINE LOADS THE FILE FROM DISK TO BUFFER MEMORY*/ opnfile() { char var_nam, name[16],*ptrr; extern char *alloc( ); unsigned int fd, endpos, begpos, count, numd; unsigned int; int num_read, i, numr; printf(“Enter name of file to ...
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AMD unsigned char temp; array[0]=0x9 array[1]=0xC0; array[2]=0x4 array[3]=0x20; array[4]=0x1; array[5]=0x40; array[6]=0x3; array[7]=0xFC; array[8]=0x5; array[9]=0x63; array[10]=0x6; array[11]=0x02; array[12]=0x7; array[13]=0x7E; array[14]=0x9; array[15]=0x02; array[16]=0xA; array[17]=0x00; array[18]=0xB; array[19]=0x08; array[20]=0xE; array[21]=0x00; array[22]=0x3; array[23]=0xFD; array[24]=0x5; array[25]=0x6B; array[26]=0x00; array[27]=0x80; array[28]=0x1; array[29]=0xC0; array[30]=0xF; array[31]=0x08; array[32]=0x0; array[33]=0x10; array[34]=0x0; array[35]=0x10; ...
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SCC Application Notes unsigned int lsb, temp, msb, latch, wrdh, wrdl, tmp1, start; unsigned int bytn, byt, tmp2; outportb(0x09, 0x01); /*clear all DMA requests on channel 1*/ outportb(0x0A, 0x05); /*mask channel 1 DMA request*/ outportb(0x0B, 0x49); /*mode register for single ...
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AMD { unsigned long int count; count = 0; while(count<35550) { count++; } } CHRONOUS TRANSMIT*/ asccinit() { unsigned char array[arraysiz], temp; unsigned int i=0; array[0]=0x09; array[1]=0xC0; array[2]=0x4; array[3]=0x44; array[4]=0x3; array[5]=0xC0; array[6]=0x5; array[7]=0x60; array[8]=0xB; array[9]=0x56; array[10]=0xC; array[11]=0x06; array[12]=0xD; array[13]=0x00; array[14]=0xE; ...
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SCC Application Notes outportb(aportd, *ptr++); } } /*TRANSMIT LENGTH OF FILE ASYNCHRONOUSLY AT 19.2 kBaud*/ trnum() { unsigned char tmp, temp, tx; unsigned int i, count; for (i=0; i<0x03; i++) { while(tx==0) temp = 0; temp = ...
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AMD Software to Receive Data at 1 Mb/s using DMA #include “stdio.h” #define arraysize 40 #define port 0x0382 #define aport 0x0380 #define aportd 0x0381 #define arraysiz 22 char *ptr; unsigned int segread(); struct{int scs, sss, sds, ses; } rv; unsigned ...
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SCC Application Notes var_nam = scanf(“%s”, string1); result = strcmp(string1,”N”); res = strcmp(string1,”n”); } while(result!=0 && res!=0); } /*THIS ROUTINE SETS A VALUE FOR THE STARTING ADDRESS AND ALLO- CATES SPACE IN MEMORY TO ACCOMMODATE ENTIRE LENGTH OF FILE*/ opnfile() ...
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AMD array[23]=0xFD; array[24]=0x5; array[25]=0x6B; array[26]=0x00; array[27]=0x80; array[28]=0x1; array[29]=0xE0; array[30]=0xF; array[31]=0x00; array[32]=0x0; array[33]=0x10; array[34]=0x0; array[35]=0x10; array[36]=0x1; array[37]=0xE0; array[38]=0x9; array[39]=0x02; /*The following dummy read statement is used to ensure that SCC has initialized properly*/ temp = inportb(port); while(i<arraysize) { outportb(port, array[i++]); } ...
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SCC Application Notes unsigned int fd; int num_wr; ptr = ptr + 3; num = num – 3; printf(“What shall I name the received file?”); var_nam = scanf(“%s”, name creat(name, BWRITE); if(fd<0) abort(“\ncreat error occured\n”); num_wr = write(fd, ...
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AMD inportb(port); outportb(port, 0x01); temp = inportb(port); while(count<300 temp & 0x80 /*THIS ROUTINE LOADS THE LENGTH OF THE FILE TO BE RECEIVED*/ length() { unsigned int *iptr; ptr++; iptr = ptr; num = *iptr; } /*THIS ...
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SCC Application Notes for(i=0; i < num; i++)/*process the loop until all char are { while(rx==0) { temp = inportb(aport);/*load RR0 to check for rec. char available temp & 0x01; *ptr = inportb(aportd);/*Input a char ...