AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 61

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Data Communication Modes Functional Description
The Parity Error bit in the Receive Error FIFO may be programmed to cause a Special
Condition interrupt by setting bit D2 of WR1 to ‘1’. If this interrupt mode is programmed,
and a Parity Error is detected, an interrupt will not be generated until the character asso-
ciated with the Parity Error is read from the Receive Data FIFO. This, or any, Special
Condition interrupt locks up the Data FIFO, and the Parity Error bit remains latched until
an Error Reset command is issued by the processor via WR0.
If interrupts are not being used to transfer data (i.e., Receive Interrupts Disabled mode)
an interrupt will not be generated and any error status must be obtained by polling RR0,
or reading RR2 (channel B). In this case, if status is to be checked, it must be done be-
fore the data are read, because the act of reading the data moves the next character and
status to the top of the Data and Error FIFOs. Note that Parity is normally not used in
SDLC modes.
4.4.3
The SCC provides up to three Modem control signals associated with the receiver in
Asynchronous mode, and two in SDLC and Synchronous modes.
In Asynchronous Mode, the SYNC pin is a general-purpose input whose state is reported
via the SYNC/HUNT status bit in RR0; however, if the crystal oscillator is enabled, this pin
is not available and the SYNC/HUNT status bit is forced to ‘0’. Otherwise, the SYNC pin
may be used to carry the Ring Indicator signal. In SDLC and Synchronous modes, except
for External SYNC mode, the SYNC pin is configured as an output.
The DTR/REQ pin carries the inverted state of the DTR bit in WR5 (D7) unless this pin
has been programmed to carry a DMA Request signal. The DCD pin is ordinarily a gen-
eral purpose input to the DCD status bit in RR0. However, if the Auto Enables mode is
selected (by setting D5 of WR3 to ‘1’), this pin becomes an enable for the receiver. That
is, if Auto Enables is on and the DCD pin is HIGH the receiver will be disabled; while the
DCD pin is LOW the receiver will be enabled. Note, however, that in all modes of opera-
tion, the Receiver Enable bit must be set before the DCD pin can be used in this manner.
4.5
The transmitter performs all the necessary functions to convert parallel data from the
processor into the appropriate serial bit streams. The transmit data path is shown in Fig-
ure 4–8.
The transmitter has an 8-bit Transmit Data register (WR8) which is loaded from the inter-
nal data bus, and a Transmit Shift Register which is loaded from either WR6, WR7, or the
Transmit Data Register (WR8).
Serial data transitions on the falling edge of TRxC begin when data written to WR8 are
transferred to the Transmit Shift Register. Each time a character is transferred from WR8
into the Transmit Shift Register a Transmit Buffer Empty indication is given via bit D2 of
RR0. This double buffering allows the processor one full character time to respond with
the next character without interrupting data transmission.
In all modes of operation, data will be sent low-order bits first (i.e. D0 before D1, etc.) for
as many bits as programmed. This requires that data written to the Transmit Buffer be
right-justified if character length is less than eight bits.
4.5.1
The number of bits transmitted per character and the way the data are formatted within
the transmit buffer is controlled by bits D6 and D5 of WR5. These bits provide the option
of five, six, seven, or eight bits per character. Being able to transmit less than five bits per
character is possible on the SCC if the five bits per character length is programmed and
the data are formatted before being written to the transmit buffer, as shown in Table 4–1,
to inform the SCC of the actual number of bits to be transmitted.
Rx Modem Control
TRANSMITTER OVERVIEW
Tx Character Length
AMD
4–9