AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 92

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
Beyond this point the receiver and transmitter are again completely independent, except
that the character boundaries are now aligned. This is shown in Figure 4–25.
There are several restrictions on the use of this feature. First, it will work only with 6-bit,
8-bit or 16-bit sync characters, and the data character length for both the receiver and the
transmitter must be six bits with a 6-bit sync character or eight bits with an 8-bit or 16-bit
sync character. Of course, the receive and transmit clocks must have the same rate as
well as the proper phase relationship.
A specific sequence of operations must be followed to synchronize the transmitter to the
receiver. Both the receiver and transmitter must have been initialized for operation in Syn-
chronous mode sometime in the past, although this initialization need not be redone each
time the transmitter is synchronized to receiver. The transmitter is disabled by setting bit
D3 of WR5 to ‘0’. At this point the transmitter will send continous ‘1’s. If it is desired that
continous ‘0’s be transmitted, the Send Break bit (D4) in WR5 should be set to ‘1’. The
transmitter is now idling but must still be placed in the Transmitter to Receiver Synchroni-
zation mode. This is accomplished by setting the Loop Mode bit (D1) in WR10 and then
enabling the transmitter by setting bit D3 of WR5 to ‘1’. At this point the processor should
set the Go Active On Poll bit (D4) in WR10. The final step is to force the receiver to
search for sync characters. If the receiver is currently disabled the receiver will enter Hunt
mode when it is enabled by setting bit D0 of WR3 to ‘1’. If the receiver is already enabled
it may be placed in Hunt mode by setting bit D4 of WR3 to ‘1’. Once the receiver leaves
hunt mode the transmitter is activated on the following character boundary.
4.10.2.4.1 Transmitter Disabling
In Synchronous modes, if the transmitter is disabled during transmission of a character,
that character will be completely sent before mark idling the line. This applies to both data
and sync characters. However, if the transmitter is disabled during the transmission of
CRC, CRC transmission will be terminated and the remaining bits will be from WR6 and/
or WR7 (sync registers) before mark idling the line.
4.10.2.5
For those applications that may want to use external logic for receiver sychronization, the
SCC makes provisions for an external circuit to signal character synchronization on the
SYNC pin. This mode expects the SYNC pin to be available for use; this means that bit
D7 of WR11 should be set to ‘0’. The External SYNC message format is shown in Figure
4–26.
In this mode, the SYNC/HUNT status bit in RR0 reports the state of the SYNC pin but the
receiver must be placed in Hunt mode when the external logic is searching for a sync
character match. When the receiver is in Hunt mode and the SYNC pin is driven Low, two
receive clocks after the last bit of the sync character is received, character assembly will
begin on the rising edge of the receive clock immediately following the activation of
SYNC. This is shown in Figure 4–27. Both transitions on the SYNC pin will cause an Ex-
ternal/Status interrupt if the SYNC/HUNT IE bit is set to ‘1’.
4–40
RxD
TxD
External SYNC Mode
Figure 4–25. Transmitter to Receiver Synchronization
Direction of Message Flow
SYNC
SYNC
Data Communication Modes Functional Description
SYNC
Receiver Leaves Hunt
SYNC