AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 60

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AM8530H

Manufacturer Part Number
AM8530H
Description
Serial Communications Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet

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The character length may be changed at any time before the new number of bits have
been assembled by the receiver. Care should be exercised, however, as unexpected re-
sults may occur if not properly timed. A representative example of switching from five bits
to eight bits and back to five bits is shown in Figure 4–7.
4.4.2
In all modes of operation bit D0 (Parity Enable) of WR4 determines whether a Parity
check is done. If this bit is set to ‘1’, the receiver calculates a parity check on every char-
acter received, as selected by bit D1 (Parity Even/Odd) of WR4, and compares it with
parity check bit transmitted. If a discrepancy is found the Parity Error status bit in the Re-
ceive Error FIFO is set at the same time that the character is transferred to the Receive
Data FIFO; otherwise, the character received will be assumed to be error free.
The additional bit per character will be visible in the Receive Data FIFO if the data plus
parity is eight bits or less. The parity bit will not be visible when there are eight data bits
per character.
4–8
Change From Five to Eight
Change From Eight to Five
Rx Parity
Figure 4–6. Five Bits/Character with Parity
Time
Figure 4–7. Changing Character Length
D1 D0
Data Communication Modes Functional Description
P
13
21
29
34
39
D4 D3 D2 D1 D0
8
RECEIVE DATA BUFFER
12 11
20 19
28 27
33 32
38 37
7
6
10
18 17
26 25
31 30
36 35
5
4
9
16 15
24 23
29 28
34 32
3
8
2
7
14
22
27
31
1
6
5 BITS
8 BITS
8 BITS
5 BITS
5 BITS

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