AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 117

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Register Description
buffer or until CRC has been completely sent. This command is necessary to prevent the
transmitter from requesting an interrupt when the transmit buffer becomes empty again,
(with Transmit Interrupt Enabled) on the last data character transmitted.
Error Reset (110). This command resets the error bits in RR1. If Interrupt on First Rx
Character or Interrupt on Special Condition modes are selected and a special condition
exists, the data with the special condition is held in the receive FIFO until this command is
issued. If either of these modes is selected and this command is issued before the data
have been read from the Receive FIFO, the data are lost.
Reset Highest IUS (111). This command resets the highest priority Interrupt Under
Service (IUS) bit, allowing lower priority conditions to request interrupts. This command
allows the use of the internal daisy chain (even in systems without an external daisy
chain) and should be the last operation in an interrupt service routine.
Bits 2 through 0: Resister Selection Code
These three bits select Registers 0 through 7. With the Point High command, Registers 8
through 15 are selected.
6.2.2
Write Register 1 is the control register for the various SCC interrupt and Wait/Request
modes. Figure 6–2 shows the bit assignments for WR1.
Bit 7: WAIT/DMA Request Enable
This bit enables the Wait/Request function in conjunction with the Request/Wait Function
Select bit (D6). If bit 7 is set to ‘1’, the state of bit 6 determines the activity of the WAIT/
REQUEST pin (Wait or Request). If bit 7 is set to ‘0’, the selected function (bit 6) forces
the WAIT/REQUEST pin to the appropriate inactive state (High for Request, floating for
Wait).
Bit 6: WAIT/DMA Request Function
The request function is selected by setting this bit to ‘1’. In the DMA Request mode, the
WAIT/REQUEST pin switches from High to Low when the SCC is ready to transfer data.
When this bit is ‘0’, the wait function is selected. In the Wait mode, the WAIT/REQUEST
pin switches from floating to Low when the CPU attempts to transfer data before the SCC
is ready.
Bit 5: WAIT/DMA Request On Receive Transmit
This bit determines whether the WAIT/REQUEST pin operates in the Transmit mode or
the Receive mode. When set to ‘1’, this bit allows the wait/request function to follow the
state of the receive buffer; i.e., depending on the state of bit 6, the WAIT/REQUEST pin is
active or inactive in relation to the empty or full state of the receive buffer. Conversely, if
this bit is set to ‘0’, the state of the WAIT/REQUEST pin is determined by bit 6 and the
state of the transmit buffer. (Note that a transmit request function is available on the DTR/
REQUEST pin. This allows full-duplex operation under DMA control for both channels.)
The request function may occur only when the SCC is not selected; e.g., if the internal
request becomes active while the SCC is in the middle of a read or write cycle, the exter-
nal request will not become active until the cycle is complete. An active request output
causes a DMA controller to initiate a read or write operation. If the request on Transmit
mode is selected in either SDLC or Synchronous mode, the Request pin is pulsed Low for
one PCLK cycle at the end of CRC transmission of another block of data.
In the Wait On Receive mode, the WAIT pin is active if the CPU attempts to read SCC
data that have not yet been received. In the Wait On Transmit mode, the WAIT pin is ac-
tive if the CPU attempts to write data when the transmit buffer is still full. Both situations
can occur frequently when block transfer instructions are used.
Write Register 1 (Transmit/Receive Interrupt and
Data Transfer Mode Definition)
AMD
6–7