AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 59

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Data Communication Modes Functional Description
BR Generator
Input
DPLL
RxD
ter with the Special Condition is read from the Data FIFO. Because under these condi-
tions the FIFO is locked, and prevented from being updated, the status pertinent to the
character read will be valid until an Error Reset command is issued via WR0.
4.4.1
The number of consecutive bits assembled in the Receive Shift Register that form a char-
acter in all modes of operation is controlled by bits D7 and D6 of WR3. Five, six, seven,
or eight bits per character may be selected via these two bits. The data plus parity bit (if
enabled) received are right-justified in the receive buffer as shown in Figure 4–6. The
SCC merely takes a snapshot of the receive data stream at the appropriate times, so the
“unused” bits in the receive buffer are only the bits following the character in the data
stream.
Time Constant
Upper Byte
1 Bit
16-Bit Down Counter
Rx Character Length
DPLL
MUX
Internal
TxD
Time Constant
Lower Byte
DPLL Output
NRZI Decode
Figure 4–5. SCC Receiver
Sync Register
& Zero Delete
+2
MUX
Hunt Mode (Disync)
BR Generator
Output
14-Bit Counter
10 x 19-Bit
Frame
Status
FIFO
SDLC-CRC
3 Bits
Shift Register
CRC Checker
CRC Delay
Register
Receive
(8 Bits)
(8 Bits)
Receive
FIFO
Data
I/O Data Buffer
CPU I/O
Internal Data Bus
CRC Result
Sync-
CRC
AMD
Error Logic
Receive
Receive
Error
FIFO
4–7
To
Transmi
Section