AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 50

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

I/O Programming Functional Description
(DTR/REQ)
(DTR/REQ)
(W/REQ)
(W/REQ)
D
TRxC
PCLK
3.3.9.3
On the NMOS SCC, the DMA Request function on DTR/REQ differs from the one on
W/REQ in that it does not go High immediately in response to the access which writes to
WR8. This is because the registers in the SCC are not written during the actual access,
but are delayed by some number of PCLK cycles. The DMA Request signal on DTR/REQ
follows the state of WR8 exactly while the Request signal on W/REQ goes inactive in an-
ticipation of WR8 becoming full. The timing of the Request signal on both pins is shown in
Figure 3–9.
This deactivation delay of DTR/REQ is unacceptable in applications where slower data
rates are involved relative to the processor. This delay can result in overwriting the Trans-
mit Buffer because the DMA Controller may recognize the continued active state of
DTR/REQ as a request for more data. On the CMOS SCC an option is provided that en-
ables the deactivation delay of DTR/REQ to be identical to that of the W/REQ pin. If
SDLC mode operation is selected and bit D0 of WR15 is set to ‘1’, then bit D4 of WR7’
can be used to alter the deactivation delay. While bit D4 of WR7’ is set to ‘1’, the deacti-
vation of DTR/REQ will be identical to W/REQ.
0
REQ
REQ
PCLK
REQ
REQ
– D
WR
7
DTR/REQ Deactivation Timing
Figure 3–9. DMA Request on Transmit Deactivation
Figure 3–8. DMA Request on Transmit Activation
ASYNC Modes
SYNC Modes
AMD
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