AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 12

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
In addition, the Am85C30 provides enhancements which allow it to be used more effec-
tively in high speed SDLC/HDLC applications. These enhancements include:
Other enhancements which make the Am85C30 more user friendly include:
1–4
Asynchronous capabilities:
– 5, 6, 7, or 8 bits per character
– 1, 1-1/2, or 2 stop bits
– Odd or Even Parity
– x1, 16, 32, or 64 clock modes
– Break generation and detection
– Parity, Overrun and Framing Error detection
Character-Oriented synchronous capabilities:
– Internal or external character synchronization
– 1 or 2 sync characters in separate registers
– Automatic CRC generation/detection
SDLC/HLDC capabilities:
– Abort sequence generation and checking
– Automatic zero bit insertion and deletion
– Automatic flag insertion between messages
– Address field recognition
– I-Field residue handling
– CRC generation/detection
– SDLC Loop mode with EOP recognition/loop entry and exit
Receiver data registers quadruply buffered. Transmitter data register doubly buffered
NRZ, NRZI, or FM encoding/decoding and Manchester decoding
Baud-rate generator in each channel
A DPLL in each channel for clock recovery
Crystal oscillator in each channel
Local Loopback and Auto Echo modes
– 10 x 19-bit SDLC/HDLC frame status FIFO
– 14-bit SDLC/HDLC frame byte counter
– Automatic SDLC/HDLC opening Flag transmission
– Automatic SDLC/HDLC Tx Underrun/EOM Flag reset
– Automatic SDLC/HDLC CRC generator preset
– TxD forced High in SDLC NRZI mode when in mark idle
– RTS synchronization to closing SDLC/HDLC Flag
– DTR/REQ DMA request deactivation delay reduced
– External PCLK to RTxC or TRxC synchronization requirement removed for one fourth
– Reduced Interrupt response time
– Reduced Read/Write access recovery time (Trc) to 3 PCLK best case (3 1/2 PCLK
– Improved WAIT timing
– Write data valid setup time to negative edge of write strobe requirement eliminated
– Write Registers WR3, WR4, WR5, WR10 and WR7 are readable
– Complete reception of SDLC/HDLC CRC characters
– Lower priority interrupt masking without INTACK generation
PCLK operation
worst case)
General Information