AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 116

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Register Description
AMD
Bits D7 and D6: CRC Reset Codes 0 and 1
Null code (00). This command has no effect on the SCC and is used when a write to
WR0 is necessary for some reason other than a CRC Reset command.
Reset Receive CRC Checker (01). This command is used to initialize the receive CRC
circuitry. It is necessary in synchronous modes (except SDLC) if the Enter Hunt Mode
command in Write Register 3 is not issued between received messages. Any action that
disables the receiver initializes the CRC circuitry. Also, whenever the receiver is in Hunt
mode, or whenever a flag is received, the CRC checker will be automatically reset in
SDLC mode.
Reset Transmit CRC Generator (10). This command initializes the CRC generator. It is
usually issued in the initialization routine and after the CRC has been transmitted. A
Channel Reset will not initialize the generator and this command should not be issued
until after the transmitter has been enabled in the initialization routine.
Reset Transmit Underrun/EOM Latch (11). This command controls the transmission of
CRC at the end of transmission (EOM). If this latch has been reset, and a transmit under-
run occurs, the SCC automatically appends CRC to the message. In SDLC mode with
Abort on Underrun selected, the SCC sends an abort, and Flag on underrun if the TX Un-
derrun/EOM latch has been reset.
At the start of the CRC transmission the Tx Underrun/EOM latch is set. The Reset com-
mand can be issued at any time during a message. If the transmitter is disabled this com-
mand will not reset the latch. However, if no External Status interrupt is pending, or if a
Reset External Status Interrupt command accompanies this command while the transmit-
ter is disabled, an External/Status interrupt is generated with the Tx Underrun/EOM bit
reset in RRO.
Bits D5–D3: Command Codes
Null Code (000). The Null command has no effect on the SCC.
Point High (001). This command effectively adds eight to the Register Pointer (D2–D0)
by allowing WR8 through WR15 to be accessed. The Point High command and the Reg-
ister Pointer bits are written simultaneously.
Reset External/Status Interrupts (010). After an External/Status interrupt (a change on
a modem line or a break condition, for example), the status bits in RR0 are latched. This
command enables the bits and allows interrupts to occur again as a result of a status
change. Latching the status bits captures short pulses until the CPU has time to read the
change. The SCC contains simple queuing logic associated with most of the external
status bits in RR0. If another External/Status condition changes while a previous condi-
tion is still pending (Reset External/Status Interrupts has not yet been issued) and this
condition persists until after the command is issued, this second change causes another
External/Status interrupt. However, if this second status change does not persist (there
are two transitions), another interrupt is not generated. Exceptions to this rule are detailed
in the RR0 description.
Send Abort (011). This command is used in SDLC mode to transmit a sequence of eight
to thirteen ‘1s.’ This command always empties the transmit buffer and sets Tx Underrun/
EOM bit in Read Register 0.
Enable Interrupt on Next RX Character (100). If the interrupt on the First Received
Character mode is selected, this command is used to reactivate that mode after each
message is received. The next character to enter the receive FIFO causes a Receive
interrupt. Alternatively, the first previously stored character in the FIFO will cause a Re-
ceive interrupt.
Reset Tx Interrupt Pending (101). This command is used in cases where there are no
more characters to be sent; e.g., at the end of a message. This command prevents fur-
ther transmit interrupts until after the next character has been loaded into the transmit
6–6