AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 89

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Data Communication Modes Functional Description
in the Receive Shift register. Now F is transferred to the receive data FIFO and CRC is
enabled. During the next eight-bit-times the processor reads F and leaves the CRC en-
abled. The processor is usually aware that this is the last character in the message and
so prepares to check the result of the CRC computation. However, another sixteen bit-
times are required before CRC has been calculated on all of character F. At the end of
eight-bit-times F is in the 8-bit delay and G is in the Receive Shift register. At this time G
is transferred to the Figure 4–23. SYNC Character Programming Figure 4–24. Receive
CRC Data Path for Synchronous Modes receive data FIFO. Character G must be read
and discarded by the processor. Eight bit times later H is transferred to the receive data
FIFO also. The result of a CRC calculation is latched in the receive error FIFO at the
same time as data is written to the receive data FIFO. Thus the CRC result through char-
acter F accompanies character H in the FIFO and will be valid in RR1 until character H is
read from the receive data FIFO. The CRC checker may be disabled and reset at any
time after character H is transferred to the receive data FIFO. Recall, however, that inter-
nally CRC will not be disabled until a character is loaded into the receive data FIFO so
the reset command should not be issued until after this occurs. A better alternative is to
place the receiver in Hunt mode, which automatically disables and resets the CRC
checker.
4.10.1.5.4 CRC Error
Because there is an eight bit delay between the Receive Shift Register and receive CRC
generator in Synchronous Modes, the CRC Error status bit in RR1 will not be valid until
16 bit times after the last CRC character has been loaded from the Receive Shift Register
to the Receive Data FIFO.
4.10.2
In Synchronous modes, the sync character in WR6 or the sync characters in WR6 and
WR7 are used to open a message transmission. Depending on the mode the transmitter
is in either one or two sync characters will be loaded into the Transmit Shift Register at
the beginning of a message. All data are shifted simultaneously out the transmit multi-
plexer and into the transmit CRC Generator. The result of the transmit CRC generator is
sent out the transmit multiplex when enabled.
4.10.2.1
The initialization sequence for the transmitter in Synchronous modes is: WR4 FIrst, to
select the mode, then WR10 to modify it if necessary, WR6 and WR7 to program the sync
characters, and then WR3 and WR5 to select the various options. At this point, the other
registers should be initialized as necessary. Once all of this is complete the transmitter
mark idles (i.e., TxD pin High) until the transmitter is enabled via bit D5 in WR5.
When the transmitter is enabled, it starts sending sync characters and continues to send
sync characters until a character is written to the Transmit Buffer (WR8). During this sync
idle time the CRC generator may be initialized by issuing the Reset Tx CRC Generator
command in WR0. When a character is written into WR8 and the current sync character
has been sent, the transmitter starts transmitting data. It will then set the Transmit Buffer
Empty bit each time the contents of WR8 are transferred into the Transmit Shift Register
to indicate that another character can be loaded into WR8.
4.10.2.2
Either of two CRC polynomials may be used for error detection purposes. The selection
for both the transmitter and receive is done via bit D2 of WR5. Setting this bit to ‘1’ se-
lects the CRC-16 polynomial, while setting it to ‘0’ selects the CRC-CCITT polynomial.
Transmitter Operation
Transmitter Initialization
CRC Polynomial Selection
AMD
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