AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 46

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

I/O Programming Functional Description
3.8.4
The Tx Underrun/EOM status bit is used in SDLC and Synchronous modes of operation
to control the transmission of CRC characters. This bit is set to ‘1’ when the Transmit
Buffer and Transmit Shift Register go empty and is reset to ‘0’ by issuing the Reset
Transmit Underrun/EOM command in WR0. Only the Low-to-High transition of this bit will
cause the latches to close and, if the Tx Underrun/EOM IE bit in WR15 (D6) is set to ‘1’,
cause an External/Status Interrupt to be generated.
This status bit is always set to ‘1’ in Asynchronous mode unless a Reset Transmit Under-
run/EOM command is erroneously issued. In this case, the Send Abort Command can be
used to set this bit to ‘1’ and, at the same time, cause an External/Status Interrupt.
Note that this bit will be set to ‘1’ when either of the following occurs; 1) a Send Abort
command is issued, 2) the transmitter is disabled, or 3) a Channel or Hardware Reset is
executed.
3.8.5
The CTS Status bit reports the state of the CTS input pin the last time any of the enabled
External/Status bits changed. Any transition on the CTS pin, while no other interrupts are
pending, latches the state of the CTS pin and generates an External/Status interrupt if the
CTS IE bit in WR15 is set to ‘1’. However, only an odd number of transitions on the CTS
pin while another External/Status is pending will cause an External/Status interrupt after
the Reset External/Status Interrupt command is issued.
If the CTS IE bit is reset, the CTS status merely reports the current inverted unlatched
state of the CTS pin; that is, if the CTS pin is Low, the CTS status bit will be High.
Note that after the Reset External/Status Interrupt command is issued, if the latches were
closed, they will close again if there was an odd number of transitions on the CTS pin;
they will remain open if there was an even number of transitions on the input pin.
3.8.6
The DCD Status bit reports the state of the DCD input pin the last time any of the enabled
External/Status bits changed. Any transition on the DCD pin, while no other interrupts are
pending, latches the state of the DCD pin and generates an External/Status interrupt if
the DCD IE bit in WR15 is set to ‘1’. However, only an odd number of transitions on the
DCD pin while another External/Status is pending will cause an External/Status interrupt
after the Reset External/Status Interrupt command is issued.
If the DCD IE bit is reset, the DCD status merely reports the current inverted unlatched
state of the DCD pin; that is, if the DCD pin is Low, the DCD status bit will be High.
Note that after the Reset External/Status Interrupt command is issued, if the latches were
closed, they will close again if there was an odd number of transitions on the DCD pin;
they will remain open if there was an even number of transitions on the input pin.
If careful attention is paid to details, the interrupt service routine for External/Status inter-
rupts is straightforward. To determine which bit or bits changed state, the routine should
first read RR0 and compare it to a copy from memory. For each changed bit, the appro-
priate action should be taken and the copy in memory updated. The service routine
should close with a Reset External/Status Interrupts command to re-open the latches.
The copy of RR0 in memory should always have the Zero Count bit set to ‘0’, since this
will be the state of the bit after the Reset External/Status Interrupts command at the end
of the service routine.
3.9
The SCC offers several alternatives for the block transfer of data. The various options are
selected via WR1 and WR14 as follows.
Tx Underrun/EOM
Clear to Send
Data Carrier Detect
BLOCK TRANSFERS
AMD
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