AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 73

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Data Communication Modes Functional Description
status bit may be able to provide the indication that an abort pattern was received, since
an abort condition places the receiver in Hunt mode.
4.7.1.6
Since the information field of an SDLC/HDLC frame can contain any number of bits and
not necessarily an integral number of 8-bit characters, the end of data is determined by
counting back 16 bits from the closing flag of a frame. The SCC provides three Residue
bits that can be used to indicate the boundary between the data and CRC characters in
the last few bytes read from the Receive Data FIFO. The meaning of these Residue bits
with each character length option is shown in Table 4–3. In this table “previous byte” re-
fers to the character received prior to the end of frame flag being detected.
The Residue Code bits are not loaded through the top of the Receive Error FIFO. They
change in RR1 when the last character of the frame is loaded into the Receive Data
FIFO. If there are any characters already in the Data FIFO, the Residue Code will not be
valid until the EOF status bit is set in RR1.
4.7.2
CRC error checking is done with a 16-bit CRC character inserted between the end of the
data field and the end of frame flag. In Synchronous modes, a control character is usually
used to signify when an end of message has been received (i.e., ETX, EOT, etc.). This
control character comes before the CRC characters; so on reception, the CRC calculation
can be stopped and the transmitted CRC characters are compared with the CRC charac-
ters generated by the receiver. This cannot be done in SDLC mode, since the end of
frame flag is after the CRC characters. In order to use the same core hardware configura-
tion already used in Synchronous modes, SDLC mode requires that the transmit CRC
generator be preset to all ‘1’s, and the complement of the CRC result be transmitted. On
reception, the receive CRC generator must also be preset to all ‘1’s and, when the end of
frame flag is detected, the result is checked against the bit pattern ‘0001110100001111’
to ascertain frame integrity. This is consistent with other bit-oriented protocols, such as
HDLC and ADCCP.
0
1
0
1
0
1
0
1
0
Residue
code
1
0
1
1
0
0
1
1
0
2
0
0
0
1
1
1
1
0
Residue Bits
SDLC Mode CRC Polynomial Selection
8B/C 7B/C 6B/C 5B/C
Data Bits in Previous
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
Byte
0
0
0
0
0
0
–
–
Table 4–3. Residue Codes
0
0
0
0
0
–
–
–
8B/C 7B/C 6B/C 5B/C
3
4
5
6
7
0
1
2
Data Bits in Second
1
2
3
4
5
6
0
–
Byte
0
0
1
2
3
4
–
–
2
0
0
0
1
–
–
–
8B/C 7B/C 6B/C 5B/C
8
8
8
8
8
8
8
8
Data Bits in Third
8
8
8
8
8
8
7
–
Byte
AMD
5
6
7
8
8
8
–
–
4–21
7
3
4
5
6
–
–
–