AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 163

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
7.3.4
When the SCC has been initialized and enabled, it is ready for communication. The trans-
mitter buffer and the receive FIFO are both empty. An interrupt will not be generated until
the software writes the first character to the transmit buffer. Once the first character is in
the SCC shift register, the first transmit interrupt will occur. The SCC then continues to
issue interrupts to the interrupt controller until the end of the message. At the end of the
message, a Reset Transmitter Interrupt Pending (WR0) is issued to clear the transmit
interrupt. After the last character is read into the SCC, the interrupts will cease until an-
other message is written into the transmitter.
Once an interrupt is received and the interrupt controller vectors to the interrupt routine,
RR2 is read from channel B. The value read from RR2 is the vector, including status. This
vector shows the status of the highest priority interrupt pending (IP) at the time it is read.
Once the highest priority interrupt condition is cleared, RR2 will show the status of the
next highest interrupt pending, if one is present. This allows multiple interrupts to be serv-
iced without the overhead of the interrupt acknowledge cycle of the interrupt controller.
MIE is disabled and then enabled to guarantee an edge for an edge-sensitive interrupt
controller.
The following example shows how the interrupt routine should be coded.
7–14
BEGIN:
;
;
TXEMPTY:
;
LAST:
;
;
RXFULL:
;
SPECIAL;
Interrupt Routine
INPUT
TEST
TEST
JUMP
OUT
OUT
IRET
TEST
JE
OUTPUT
DEC
JUMP
OUTPUT
JUMP
INPUT
COMPARE RR1,00
JUMP
INPUT
JUMP
.
.
This means a framing error, receive overrun error or parity error
has occurred. Character may be read but data is not correct.
A flag should be set to post the error.
.
.
OUTPUT RR0, 30H
JUMP BEGIN
JE
NOMORE
LAST
CHAR
CHARCOUNT
BEGIN
RR0,28H
BEGIN
RR1
NE
CHAR
BEGIN
RR2
Bit 4
TXEMPTY
Bit 5
RXFULL
WR9 00
EOI
Figure 7–5. SCC Interrupt Routine
;Test for Tx Empty
;Jump to Receive Routine
;MIE Disabled
;Output EOI to Interrupt Controller
;Read RR2 from channel B
;Jump to Transmit Routine
;Test for Rx full
;Return to Main
;Test a last character flag
;Jump to LAST if no more characters
;Output character to data port
;Decrement character count
;Jump to BEGIN to test for more IP
;Reset Tx Interrupt Pending
;Jump to BEGIN to test for more IP
;Read RR1
;Test for special condition bit set
;Jump to SPECIAL
;Input charcater from data port
;Jump to BEGIN to test for more IP
;Reset Error Command
;Jump to BEGIN to test for more IP
SCC Application Notes