AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 107

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Support Circuitry Programming
Correction
Windows
Receive
Length
However, if the transition marking a bit cell boundary occurs between the middle of count
16 and the middle of count 19 the DPLL is sampling the data too early in the bit cell. In
response to this the DPLL extends its count by one during the next 0 to 31 counting cycle,
which effectively moves the receive clock edges closer to to where they should be. In FM
mode any transitions occurring between the middle of count 19 in one cycle and the mid-
dle of count 12 during the next cycle are ignored by the DPLL. This is necessary to guar-
antee that any data transitions in the bit cells will not cause an adjustment to the counting
cycle.
As in NRZI mode, if an adjustment to the counting cycle is necessary, the DPLL modifies
count 5, either deleting it or doubling it. If no adjustment is necessary, the count sequence
proceeds normally. While the DPLL is in Search mode, the counter remains at count 16,
where the receive output is Low and the transmit output is Low. This fact can be used to
provide a transmit clock under software control since the DPLL is in Search mode while it
is disabled. Note that while the DPLL is disabled the transmit clock output of the DPLL
may be toggled by alternately selecting FM and NRZI mode in the DPLL. The same is
true of the receive clock.
Output
5.5.3.3
In addition to FM and NRZI encoded data, the DPLL may also be used to recover the
clock from Manchester encoded data, which contains a transition at the center of every bit
cell. Here it is the direction of the transition that distinguishes a ‘1’ from a ‘0’. Another
way of looking at Manchester encoding is to realize that, during the first half of the bit cell
the data are sent; during the second half of the bit cell the complement of the data are
sent. This is shown in Figure 5–9, along with the DPLL output if it thinks that the mid-bit
transitions are really bit cell boundaries. As is obvious from the figure, if the receiver sam-
ples the data on the falling edge of the DPLL receive clock output, the Manchester data
will be properly decoded. This occurs if the receiver is programmed to accept NRZ data.
5.5.3.4
From the above discussion together with an examination of FM0 and FM1 data encoding,
it should be obvious that only clock transitions should exist on the receive data pin when
the DPLL is programmed to enter Search mode. If this is not the case the DPLL may at-
tempt to lock on to the data transitions. With FM0 encoding this requires continuous ‘1’s
received when leaving Search mode. In FM1 encoding it is continuous ‘0’s; with
Manchester encoded data this means alternating ‘1’s and ‘0’s.
Count
DPLL
Data
32
+1
Manchester Decoding Mode
FM Mode DPLL Receive Status
–1
32
+1
–1
32
+1
Figure 5–7. DPLL in FM Mode
–1
31
+1
–1
31
+1
–1
31
+1
–1
33
+1 –1
33
+1
AMD
–1
33
5–13
+1