AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 36

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

I/O Programming Functional Description
3.4.2
The Interrupt Pending (IP) bit for a given source of interrupt may be set by the presence
of an interrupt condition in the SCC and is reset directly by the processor, or indirectly by
some action that the processor may take. If the corresponding IE bit is not set, the IP for
that source of interrupt will never be set. The IP bits in the SCC are read-only via RR3 as
shown above.
3.4.3
The Interrupt Under Service (IUS) bits are not observable by the processor. An IUS bit is
set during an Interrupt Acknowledge cycle for the highest-priority IP. The IUS bit is used
to control the operation of internal and external daisy chain interrupts. The internal daisy
chain links the six sources of interrupt in a fixed order, chaining the IUS bits for each
source. While an internal IUS bit is set, all lower-priority interrupt requests are masked
off; during an Interrupt Acknowledge cycle the IP bits are also gated into the daisy chain.
This insures that the highest-priority IP selected will have its IUS bit set. At the end of an
interrupt service routine, the processor must issue a Reset Highest IUS Command in
WR0 to re-enable lower-priority interrupts. This is the only way, short of a software or
hardware reset, that an IUS bit may be reset.
3.4.4
The Disable Lower Chain (DLC) bit in WR9 (D2) is used to disable all SCCs in a lower
position on the external daisy chain. If this bit is set to ‘1’, the IEO pin is driven Low and
prevents lower-priority devices from generating an interrupt request. Note that the IUS bit,
when set, will have the same effect but is not controllable through software, and the point
where lower-priority interrupts are masked off may not correspond to the chip boundary.
W/DMA
Enable
REQ
D7
D7
0
Interrupt Pending Bit
Interrupt Under Service Bit
Disable Lower Chain Bit
W/DMA
Funct.
REQ
D6
D6
0
REQ on
W/DMA
Rx/Tx
Ch. A
D5
Rx
D5
IP
WR1—Interrupt Source IE
RR3—Interrupt Pending
Ch. A
D4
D4
Tx
IP
0
0
1
1
Ext/Sta
Ch. A
D3
D3
IP
0
1
0
1
— Rx INT Disable
— Rx INT on 1st Char. or
— INT on All Rx Char. or
— Rx INT on Special Only
Enable
Ch. B
Parity
Special Condition
Special Condition
INT
Rx
D2
D2
IP
Enable
Ch. B
INT
Tx
D1
IP
D1
Tx
Ext/Sta
Ext/Sta
Enable
Ch. B
AMD
INT
D0
D0
IP
3–5