AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 129

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Register Description
Bits 7 and 6: Reset Command Bits
Together, these bits select one of the reset commands for the SCC. Setting either of
these bits to ‘1’ disables both the receiver and the transmitter in the corresponding chan-
nel, forces TxD for that channel marking, forces the modem control signals High in that
channel, resets all IPs and IUSs and disables all interrupts in that channel. Five extra
PCLK cycles must be allowed beyond the usual cycle time before any additional com-
mand or controls are written to the SCC.
No Reset (00). This command has no effect. It is used when a write to WR9 is necessary
for some reason other than an SCC Reset command.
Channel Reset B (01). Issuing this command causes a channel reset to be performed on
Channel B.
Channel Reset A (10). Issuing this command causes a channel reset to be performed on
Channel A.
Force Hardware Reset (11). The effects of this command are identical to those of a
hardware reset except that the MIE, Status High/Status Low and DLC bits take the pro-
grammed values that accompany this command.
Bit 5: Interrupt Masking Without INTACK
If this bit is set to ‘1’, the INTACK cycle is ignored by the SCC and should be tied High.
This allows users to mask lower priority interrupts in applications where INTACK is nei-
ther necessary nor used.
Bit 4: Status High/ Status Low
This bit controls which vector bits the SCC will modify to indicate status. When set to ‘1’,
the SCC modifies bits V6, V5, and V4 according to Table 6–4. When set to ‘0’, the SCC
modifies bits V1, V2, and V3 according to Table 6–1–3. This bit controls status in both
the vector returned during an interrupt acknowledge cycle and the status in RR2B. This
bit is reset by a hardware reset.
Bit 3: Master Interrupt Enable
The Master Interrupt Enable bit is used to globally inhibit SCC interrupts. When set to ‘1’,
interrupts for channel A and channel B are enabled. When this bit is set to ‘0’, IEO is not
forced low but follows the state of IEI unless there is an IUS set in the SCC. No IUS can
be set after the MIE bit is set to ‘0’. This bit is reset by a hardware reset.
V3
V4
0
0
0
0
1
1
1
1
V2
V5
0
0
1
1
0
0
1
1
Table 6–4. Interrupt Vector Modification
V1
V6
0
1
0
1
0
1
0
1
Status High/Status Low=0
Status High/Status Low=1
Ch B Transmit Buffer Empty
Ch B External/Status Change
Ch B Receive Character Available
Ch B Special Receive Condition
Ch A Transmit Buffer Empty
Ch A External/Status Change
Ch A Receive Character Available
Ch A Special Receive Condition
AMD
6–19