AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 31

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

System Interface
hardware reset to ensure that the FIFO is completely flushed before the new data can be
received reliably.
The SCC has three software resets encoded into command bits in WR9. There are two
channel resets, which affect only one channel in the device and some of the bits in the
write registers. The third command forces the same result as a hardware reset. As in the
case of a hardware reset, the SCC stretches the reset signal an additional four to five
PCLK cycles beyond the ordinary valid access recovery time. When the SCC is first pow-
ered up, performing a read with the D/C pin held Low will guarantee that the pointers are
reset to ‘0’; then a reset command can be issued by selecting WR9 and writing to it. The
bits in WR9 may be written at the same time as the reset command because these bits
are affected only by a hardware reset. The reset values of the various registers are
shown in Figure 2–4.
7
0 0 0 0 0 0 0 0
0 0 .
.
.
.
0 .
.
.
1 1 0 0 0 0 .
0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0
.
.
.
1 1 1 1 1 0 0 0
0 1 .
0 0 0 0 0 1 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
6
.
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Hardware Reset
5
.
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.
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.
1 0 0 0 0 0
4
0 0 .
.
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.
0 0 0 0 .
.
.
.
.
.
Figure 2–4. SCC Register Reset Values
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3
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1
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1 0 0
2
0 0
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1
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0
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0
7
0 0 0 0 0 0 0 0
0 0 .
0 .
.
0 .
.
1 1 1 1 1 0 0 0
0 1 .
0 0 0 0 0 1 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
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6
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Channel Reset
5
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0
.
1 0 0 0 .
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4
0 0 .
0 0 0 0 .
0 0 0 0 0
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3
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1
1 0 0
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2
0 0
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1
0
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0
WR0
WR1
WR2
WR3
WR4
WR5
WR6
WR7
WR9
WR10
WR11
WR12
WR13
WR14
WR15
RR0
RR1
RR3
RR10
AMD
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