AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 146

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
6.3.5
When the SCC is programmed for SDLC operation and bit D2 of WR15 is set to ‘1’, RR6
contains the LSB of a frame byte count stored in the 10x19-bit FIFO array as shown in
Figure 6–22.
6.3.6
When the SCC is programmed for SDLC operation and bit D2 of WR15 is set to ‘1’, RR7
contains the MSB of a frame byte count stored in the 10x19-bit FIFO array, and provides
FIFO status via bits D7 and D6 as shown in Figure 6–23. Bit D7 is set to ‘1’ when the
10x19-bit FIFO overflows; otherwise it is set to ‘0’. Bit D6 is used to determine if status
data will be from the FIFO or directly from the 8-bit Status FIFO (RR1). This bit is set to
‘1’ whenever the 10x19-bit FIFO is not empty; otherwise it is ‘0’.
6–36
D
7
D
D
7
Read Register 6
Read Register 7
6
D
D
6
5
D
D
5
4
D
D
4
3
D
D
3
2
D
Figure 6–21. Read Register 3
Figure 6–22. Read Register 6
D
Figure 6–23. Read Register 7
7
D
2
1
D
D
D
6
1
0
D
D
0
Channel B EXT/STAT IP
Channel B Tx IP
Channel B Rx IP
Channel A EXT/STAT IP
Channel A Tx IP
Channel A Rx IP
0
0
5
MSB Byte Count
FIFO Data Available Status
FIFO Overflow Status
D
4
1 = Status Reads Come From 10 x 9 Bit FIFO
0 = Status Reads Come From SCC
1 = FIFO Overflowed During Operation
0 = Normal
D
3
D
2
D
1
D
0
Register Description
Always 0 in B Channel