AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 158

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

SCC Application Notes
7.2.3.1
WR9 resets the SCC to a known state by writing a C0 hex. The Force Hardware Reset
command is identical to a hardware reset. It will reset both channels.
WR4 selects the Asynchronous, x 16 mode, with 2 stop bits and no parity. The x 16 mode
means that clock rate is 16 times the data rate.
WR3 selects 8 bits per character and does not enable the receive. The 8 bits per charac-
ter allows 8 bits to be assembled from the data stream. The receiver is not enabled at this
time because the SCC has not been initialized.
WR5 selects 8 bits per character and does not enable the transmitter. The 8 bits per char-
acter allows 8 bits to be sent, as data, with the least significant bit first. The transmitter is
not enabled at this time because the SCC has not been initialized.
WR9 selects that there are no interrupts enabled. This inhibits the SCC from requesting
an interrupt from the CPU.
WR10 selects NRZ encoding. This NRZ coding is used on the transmitter as well as the
receiver.
WR11 selects the RTxC pin to TTL clock; the baud-rate generator is the transmit and re-
ceive clocks source, and the TRxC pin is used as a baud-rate generator output.
WR12 & WR13 select the baud-rate generator’s time constant. The WR13 time constant
is determined by the equation:
In this example, the clock frequency is 2.4576 MHz, the baud rate is 9600, the clock
mode is 16. The time constant is, therefore, 6; expressed as a 16-bit, hexadecimal num-
ber, it is 0006H. The time constant Low (WR12) is, therefore 06H and the time constant
High (WR13) is 00H. The baud rate for this example can be varied, as long as the data
rate is less than
mon baud rates.
SCC Operating Mode Programming
Time Constant =
Register
WR9
WR4
WR3
WR5
WR9
WR10
WR11
WR12
WR13
WR14
Enables
WR14
WR3
WR5
Table 7–4. Polled Asynchronous Initialization Procedure
1
/
4
of the PCLK rate. Table 7–5 shows the time constants for other com-
Value
C0H
4CH
C0H
C1H
60H
00H
00H
56H
06H
00H
10H
11H
68H
2 x Baud Rate x clock mode
Comments
Force Hardware Reset
x16 clock, 2 stop bits, no parity
Rx 8 bits, Rx disabled
Tx 8 bits, DTR, RTS, Tx off
Int. Disabled
NRZ
Tx & Rx = BRG out, TRxC = BRG out
Time constant = 6
Time constant high = 0
BRG in = RTxC, BRG off, loopback
BRG enable
Rx enable
Tx enable
Clock Frequency
–2
AMD
7–9