AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 68

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
In SDLC Mode the Following Definitions Apply
• All Sent Bypasses MUX and Equals Contents of SCC Status Register
• Parity Bits Bypasses MUX and Does the Same
• EOF is Set to 1 Whenever Reading from the FIFO
When this FIFO is enabled, RR6 accommodates the LSB byte count from the 14-bit byte
counter and RR7 accommodates the MSB byte count along with FIFO availability and
Overflow status. Figure 4–13 shows the details of these registers including WR15.
If frame status is to be acquired from the 10x19-bit FIFO, it must be enabled and not
empty, and the registers must be read in the following order: RR7, RR6, and RR1 (read-
ing RR6 is optional). Accessing RR7 latches the FIFO Empty/Full status bit (D6 of RR7)
and steers the status multiplexer to read from the 10x19-bit FIFO array instead of from
the 8-bit Status FIFO.
Reading RR1 immediately after RR7 causes one location of the FIFO to be emptied, so
status should be read after reading the byte count; otherwise, the count will be incorrect.
If the FIFO goes empty when RR1 is read, the FIFO is disabled and the next read of RR1
will be directly from the 8-bit status FIFO, and reads from RR7 and RR6 will contain bits
that are undefined. To determine if status data is coming from the 10x19-bit FIFO or di-
rectly from the status register the user should check bit D6 of RR7. If this bit is set to ‘1’
the FIFO is not empty; if set to ‘0’ the FIFO is empty.
2 Bits
4–16
RR1
Interface to SCC
6-Bit MUX
SCC Status Reg
Residue Bits(3)
Overrun
CRC Error
(Existing)
6 Bits
RR1
5 Bits
10 x 19-Bit FIFO Array
6 Bits
EOF = 1
Figure 4–12. 10x19-Bit Frame Status FIFO
Bit 7
FIFO Overflow Status Bit
MSB of RR(7) is Set on Status FIFO
Overflow
Bit 6
FIFO Data Available Status Bit
Status Bit Set to 1
When Reading From FIFO
Data Communication Modes Functional Description
14-Bit Byte Counter
6 Bits
Bits 0-5
RR7
14 Bits
Byte Counter Contains 14 Bits for
a 16-Kbyte Maximum Count
8 Bits
RR6
EN
Reset on Flag Detect
Increment on Byte DET
Enable Count in SDLC
End of Frame Signal
Status Read Comp
4-Bit Comparator
Over
4-Bit Counter
Head Pointer
4-Bit Counter
Tail Pointer
Equal
FIFO Enable
WR(15) Bit 2
Set Enables
Status FIFO