AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 155

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
7.1.1.3
Table 7–1 as shown previously, is a worksheet for the initialization of the SCC. All the bits
that must be programmed as either a ‘0’ or a ‘1’ are already filled in; the remaining bits
are left blank and are to be programmed by the user according to the desired mode of
operation. The binary value can then be converted to a hexadecimal number and placed
in the table, following the Write register notation in the column labeled “HEX.” A Program
Initialization Table is produced when this worksheet is completed.
7.1.1.4
Prior to initialization, the SCC should be reset by either hardware or software. A hardware
reset can be accomplished by simultaneously grounding RD and WR. A software reset
can be executed by writing a C0H to Write Register 9. After one channel has been initial-
ized, a channel reset should be used in place of the hardware reset in the initialization.
The state of the SCC registers, after reset, is shown in Table 7–3. Before writing to the
SCC, a read should be performed to guarantee the internal logic is pointing to Register 0.
7–6
Initialization Table Generation
Reset Conditions
1 = Set to one
0 = Reset to zero
prog.
WR9
WR4
WR1
WR2
WR3
WR5
WR6
WR7
WR9
WR10
WR11
WR12
WR13
WR14
WR14
WR14
WR3
WR5
WR0
WR1
WR15
WR0
WR0
WR1
WR9
Table 7–2. SCC Initialization Order
1100000
XXXXXXXX Tx/Rx con, Aysnc or Sync Mode
0XX00X00 Select W/REQ (opt)
XXXXXXXX Program Interrupt Vector (opt)
XXXXXXX0 Select Rx Control
XXXX0XXX Select Tx Control
XXXXXXXX Program sync character (opt)
XXXXXXXX Program sync character (opt)
000X0XXX Select Interrupt Control
XXXXXXXX Miscellaneous Control (opt)
XXXXXXXX Clock Control
XXXXXXXX Time constant lower byte (opt)
XXXXXXXX Time constant upper byte (opt)
XXXXXXX0 Miscellaneous Control
XXXSSSSSCommands (opt)
000SSSS1 Baud Rate Enable
SSSSSSS1 Rx Enable
SSSS1SSS Tx Enable
10000000 Reset Tx CRG (opt)
XSS00S00 DMA Enable (opt)
XXXXXXXX Enable External/Status
00010000 Reset External Status
00010000 Reset External Status twice
SSSXXSXX Enable Rx, Tx and Ext/Status
000SXSSS Enable Master Interrupt Enable
Part 1. Modes and Constants
Part 3. Interrupt Status
Part 2. Enables
X = User defined
S = Same as previously
Hardware Reset
SCC Application Notes