AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 118

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
Bits 4 and 3: Receive Interrupt Modes
These two bits specify the various character-available conditions that may cause interrupt
requests.
Receive Interrupts Disabled (00). This mode prevents the receiver from requesting an
interrupt and is normally used in a polled environment where either the status bits in RR0
or the modified vector in RR2 (Channel B) can be monitored to initiate a service routine.
Although the receiver interrupts are disabled, a special condition can still provide a unique
vector status in RR2.
Receive Interrupt on First Character or Special Condition (01). The receiver requests
an interrupt in this mode on the first available character (or stored FIFO character) or on a
special condition. Sync characters to be stripped from the message stream do not cause
interrupts.
Special receive conditions are: receiver overrun, framing error, end of frame, or parity
error (if selected). If a special receive condition occurs, the data containing the error are
stored in the receive FIFO until an Error Reset command is issued by the CPU.
This mode is usually selected when a Block Transfer mode is used. In this interrupt
mode, a pending special receive condition remains set until either an Error Reset com-
mand, a channel or hardware reset, or until receive interrupts are disabled.
The Receive Interrupt on First Character or Special Condition mode can be re-enabled by
the Enable Rx Interrupt on Next Character command in WR0.
Interrupt on All Receive Characters or Special Condition (10). This mode allows an
interrupt for every character received (or character in the receive FIFO) and provides a
unique vector when a special condition exists. The Receiver Overrun bit and the Parity
Error bit in RR1 are two special conditions that are latched. These two bits must be reset
by the Error Reset command. Receiver overrun is always a special receive condition, and
parity can be programmed to be a special condition.
Data characters with special receive conditions are not held in the receive FIFO in the
Interrupt On All Receive Characters or Special Conditions mode as they are in other re-
ceive interrupt modes.
6–8
D
7
D
6
D
5
D
0
0
1
1
4
D
0
1
0
1
3
D
Rx INT Disable
Rx INT on First Character or Special Condition
INT on All Rx Characters or Special Condition
Rx INT on Special Condition Only
2
Figure 6–2. Write Register 1
D
1
D
0
EXT INT Enable
Tx INT Enable
Parity is Special Condition
WAIT/DMA Request on RECEIVE/TRANSMIT
WAIT/DMA Request Function
WAIT/DMA Request Enable
Register Description