AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 172

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AM8530H

Manufacturer Part Number
AM8530H
Description
Serial Communications Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet

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SCC Application Notes
7.5.3
The following description addresses the problems of interfacing the 68000 and Am8530H
with interrupts. The circuit configuration is basically the same as the design without inter-
rupts.
The 74LS148 and the two 74LS138s assume there are other interrupting devices which
are not compatible with the interrupt daisy chain of the Am8530H. The 74LS148 and one
of the 74LS138 can be eliminated if this is not the case.
The first 74LS138 acts as a status decoder; it is gated with AS to de-glitch the outputs.
The second 74LS138 decodes the Interrupt Acknowledge priority level, allowing a two-
dimensional priority scheme. Daisy chain can be used to resolve priority at any given pri-
ority level while the CPU resolves priority between levels.
The 74LS164 is added to generate the correct timing during an Interrupt Acknowledge
cycle. It allows 5 CPU clocks for the daisy chain to settle before it generates RD to put the
vector onto the bus. The daisy chain is implemented by using the IEI, IEO pins (not
shown in Figure 7–12) on the 8500 peripherals. The time allowed for the daisy chain to
settle is a function of the number of devices in the chain; thus the allowance of 5 clocks
used here is arbitrary. The 74LS164 also generates DTACK. A block diagram of this inter-
face is shown in Figure 7–15. Timing diagram is followed in Figure 7–13. It is more
straightforward to use the Am9519A Interrupt Controller instead of the on-chip interrupt
features. However, this approach does not allow the programmer to take advantage of
some of the Am8530H time-saving features.
FC0–FC02
A 1 - A 3
DTACK
IACK
RD
AS
Figure 7–13. Am8530H to 68000 Interrupt Acknowledge Timing
The 68000 and Am8530H with Interrupts
S 0 S 1 S 2 S 3 S 4
T 1
T 2
T W
S W
S W S W S W S W S W S W S W S W S W S W S 6 S 7 S 0
T W
T W
T W
DATA IN
T W
T 3
READ
DATA
T 4
AMD
7–23

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