AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 69

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Data Communication Modes Functional Description
Since not all status bits of RR1 are stored in the Frame Status FIFO, the All Sent, Parity,
and EOF bits bypass the FIFO and are stored in the 8-bit Status FIFO. The status bits
stored in the 10x19-bit FIFO will be the Residue, Overrun, and CRC status bits. Note that
the EOF interrupt is generated the same way as before.
4.7.1.3.3
When an EOF is detected, and the FIFO is enabled, the five status bits and byte-count
are loaded into the FIFO, and the FIFO pointer is incremented. If the FIFO overflows, bit
D7 of RR7 (FIFO Overflow) is set to indicate the overflow. This bit and the FIFO control
logic is reset by disabling and re-enabling the FIFO control bit (WR15 bit D2). For details
of FIFO control timing during an SDLC frame, refer to Figure 4–14.
When a packet is completely received, then a Receive Interrupt on Special Condition is
generated upon receipt of the End of Frame Flag. If the clock is temporarily stopped after
the receipt of the flag, the Frame Status FIFO may not be updated even though the inter-
rupt was generated. At least two receive clocks are needed to update the Frame Status
FIFO. The Frame Status information is not lost and will be put into the Frame Status FIFO
when the clock is enabled again.
4.7.1.3.4
The 14-bit byte counter allows for data frames of up to 16K bytes to be received. It is en-
abled when bit D2 of WR15 is set to ‘1’ and the SCC is in SDLC mode. It is reset when-
ever an SDLC flag character is received. The reset is timed so that the contents of the
byte counter are successfully written into the FIFO.
The byte counter is incremented by writes to the 8-bit receive Data FIFO. The counter
represents the number of bytes received by the SCC, rather than the number of bytes
transferred from the SCC. (These counts may differ by up to the number of bytes in the
receive data FIFO contained in the SCC.)
WR16
RR7
RR6
FIFO Write Operation
14-Bit Byte Counter
FOY
7
7
BC
7
7
*
FDA
6
BC
6
6
6
Figure 4–13. Frame Status FIFO Registers
*
BC
13
5
BC
5
5
5
*
FIFO Data Available Status
1 = Status Reads Will Come From FIFO
0 = Status Reads Will Come From SCC
FIFO Overflow Status
1 = FIFO Overflowed During Operation
0 = Normal
BC
12
4
BC
4
4
4
*
BC
11
3
BC
3
3
3
*
BC
10
FEN
2
BC
2
2
2
BC
1
9
BC
1
1
1
*
Status FIFO Enable Control Bit
1 =
0 =
* =
0
BC
8
BC
0
0
0
*
Status and Byte Count Will be
Held in the Status FIFO Until Read
Status Will Not be Held (SCC)t
(Emulation Mode)
No Change From NMOS SCC DFN
Read From FIFO
LSB Byte Count
10216A-013A
AMD
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