AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 121

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Register Description
Bit 2: Address Search Mode (SDLC)
Setting this bit in SDLC mode causes messages with addresses not matching the ad-
dress programmed in WR6 to be rejected. No receiver interrupts can occur in this mode
unless there is an address match. The address that the SCC attempts to match can be
unique (1 in 256) or multiple (16 in 256), depending on the state of Sync Character Load
Inhibit bit. The Address Search mode bit is ignored in all modes except SDLC.
Bit 1: SYNC Character Load Inhibit
If this bit is set to ‘1’ in any synchronous mode except SDLC, the SCC compares the byte
in WR6 with the byte about to be stored in the FIFO, and it inhibits this load if the bytes
are equal. The SCC does not calculate the CRC on bytes stripped from the data stream
in this manner. If the 6-bit sync option is selected while in Monosync mode, the compare
is still across eight bits, so WR6 must be programmed for proper operation.
If the 6-bit sync option is selected with this bit set to ‘1’, all sync characters except the one
immediately preceding the data are stripped from the message. If the 6-bit sync option is
selected while in the Bisync mode, this bit is ignored.
The address recognition logic of the receiver is modified in SDLC mode if this bit is set to
“1;” i.e., only the four most significant bits of WR6 must match the receiver address. This
procedure allows the SCC to receive frames from up to 16 separate sources without pro-
gramming WR6 for each source (if each station address has the four most significant bits
in common). The address field in the frame is still eight bits long.
This bit is ignored in SDLC mode if Address Search mode has not been selected.
Bit 0: Receiver Enable
When this bit is set to ‘1’, receiver operation begins. This bit should be set only after all
other receiver parameters are established and the receiver is completely initialized. This
bit is reset by a channel or hardware reset command, and it disables the receiver.
6.2.5
WR4 contains the control bits for both the receiver and the transmitter. These bits should
be set in the transmit and receiver initialization routine before issuing the contents of
WR1, WR3, WR6, and WR7. Bit positions for WR4 are shown in Figure 6–5. This register
is readable by executing a read to RR4 when D0 of WR15 and D6 of WR7 are set to ‘1’.
Write Register 4 (Transmit/Receiver Miscellaneous
Parameters and Modes)
D
0
0
1
1
7
D
0
1
0
1
6
D
Rx 5 Bits/Character
Rx 7 Bits/Character
Rx 6 Bits/Character
Rx 8 Bits/Character
5
D
4
Figure 6–4. Write Register 3
D
3
D
2
D
1
D
0
Rx Enable
SYNC Character Load Inhibit
Address Search Mode (SDLC)
Rx CRC Enable
Enter Hunt Enable
Auto Enables
AMD
6–11