AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 115

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Register Description
6.2
The SCC write register set for each channel includes ten control registers, two sync char-
acter registers, two baud rate time constant registers, a transmit buffer, and a master in-
terrupt register. The following sections describe in detail each write register and the
associated bit configuration for each.
6.2.1
WR0 is the command register and the CRC reset code register. Figure 6–1 shows the bit
configuration for WR0.
WRITE REGISTERS
Write Register 0 (Command Register)
D
0
0
1
1
7
D
0
1
0
1
6
Null Code
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
D
0
0
0
0
1
1
1
1
5
D
0
0
1
1
0
0
1
1
4
D
0
1
0
1
0
1
0
1
3
Figure 6–1. Write Register 0
D
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Null Code
Point High
Reset EXT/Status Interrupts
Send Abort (SDLC)
Enable INT On Next Rx Character
Reset TxINT Pending
Error Reset
Reset Highest IUS
2
D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
Register 14
Register 15
With Point High Command
AMD
6–5