AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 145

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Register Description
Bit 0: All Sent
In Asynchronous mode, this bit is set when all characters have completely cleared the
transmitter. Most modems contain additional delays in the data path, which require the
modem control signals remain active until after the data have cleared both the transmitter
and the modem. This bit is always set in synchronous and SDLC modes.
6.3.3
RR2 contains the interrupt vector written into WR2. When the register is accessed in
Channel A, the vector returned is the vector actually stored in WR2. When this register is
accessed in Channel B, the vector returned includes status information in bits 1, 2, and 3
or in bits 6, 5, and 4, depending on the state of the Status High/Status Low bit in WR9
and independent of the state of VIS bit in WR9. The vector is modified according to Table
6–4 shown in the explanation of the VIS bit in WR9. If no interrupts are pending, the
status is V3, V2, V1 = 011, or V6, V5, V4 = 110. Only one vector register exists in the
SCC, but it can be accessed through either channel. Figure 6–20 shows the bit positions
for RR2.
*Modified in B Channel
6.3.4
RR3 is the Interrupt Pending register. The status of each of the Interrupt Pending bits in
the SCC is reported in this register. This register exists only in Channel A. If this register
is accessed in Channel B, all ‘0’s are returned. The two unused bits are always returned
as ‘0’. Figure 6–21 shows the bit positions for RR3.
Read Register 2
Read Register 3
Bits/Char
8
7
6
5
D
7
Table 6–10. Residue Bits/Character
D
6
Figure 6–20. Read Register 2
D
5
Residue
D
4
0
0
0
0
0
D
3
D
2
D
Residue
1
D
1
1
0
1
0
0
V
V
V
V
V
V
V
V
0
1
2
3
4
5
6
7
Residue
Interrupt Vector*
2
1
0
0
1
AMD
6–35