AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 91

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Data Communication Modes Functional Description
The Tx Underrun/EOM status bit in RR0 will be set to ‘1’ to indicate that an underrun has
occurred, and that the CRC, or sync characters, have been loaded into the Transmit Shift
Register for transmission. The Low-to-High transition of this bit may be programmed to
generate an External/Status interrupt or, if interrupts are disabled, may be polled in RR0.
Hence, if the CRC check characters are to be properly appended to the end of a mes-
sage, the Reset Tx Underrun/EOM Command must be issued after the first, but before
the last, character is written to the Transmit Buffer.
Note that the Reset Tx Underrun/EOM command will not reset the status bit latch if the
Transmitter is disabled. However, if no External/Status interrupts are pending, or if a Re-
set External/Status Interrupt command accompanies this command while the transmitter
is disabled, an External/Status interrupt will be generated with the Tx Underrun/EOM bit
reset in RR0.
4.10.2.2.4 Tx CRC Character Exclusion
On the SCC, leading sync characters are automatically excluded from CRC calculation,
but it will be calculated on any sync characters sent as data unless the transmit CRC gen-
erator is disabled via bit D0 of WR5 when that character is loaded in the Transmit Shift
Register from the Transmit Buffer.
Internally, the CRC is enabled or disabled for a particular character at the same time as
the character is loaded from the Transmit Buffer to the Transmit Shift Register. Thus, to
exclude a character from CRC calculation, bit D0 of WR5 should be set to ‘0’ before the
character is written to the transmit buffer. This guarantees that the internal disable will
occur when the character moves from the buffer to the shift register. Once the buffer be-
comes empty, the Tx CRC Enable bit may be set for the next character.
4.10.2.3
The SCC can be used in applications where data are sent without enveloping them in any
specific protocol or Parity. This can be done by programming WR4 for the channel in Ex-
ternal SYNC mode as shown below.
In this mode of operation, the transmitter will be configured for MONOSYNC operation
and the SYNC pin will be used to signal when to start reception of data. The transmitter is
initialized as before except that the first character to be sent must be written to WR6 be-
fore enabling the transmitter. Once the transmitter is enabled and transmission of the
character in WR6 has started, the Transmit Buffer can be written to with the next charac-
ter. From that point on, data from the Transmit Buffer will continue to be sent until the
transmitter is disabled. To prevent any unwanted data in WR6 from being sent when a
transmitter underrun occurs, the transmitter must be disabled during the transmission of
the last character. The same procedure is followed if another data block is to be sent.
Data reception in this mode of operation requires that the SYNC pin be used to signal
when character accumulation should commence at the receiver. As long as SYNC re-
mains Low data will continue to be received and transferred.
4.10.2.4
The SCC contains a transmitter-to-receiver synchronization function that may be used to
guarantee that the character boundaries for the received and transmitted data are the
same. In this mode the receiver is in Hunt and the transmitter is idle, sending either all
‘1’s or all ‘0’s. When the receiver recognizes a sync character, it leaves Hunt mode and
one character time later the transmitter is enabled and begins sending sync characters.
Transparent Transmission
Transmitter to Receiver Synchronization
0
WR4—Register Layout
0
1
1
0
0
X
0
AMD
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