AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 22

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
** Only available in Am85C30.
2–4
Read Register Functions
RR0
RR1
RR2
RR3
*RR6
*RR7
RR8
RR10
RR12
RR13
RR15
* Available only when Am85C30 is programmed in enhanced mode.
Write Register Functions
WR0
WR1
WR2
WR3
WR4
WR5
WR6
WR7
**WR7
WR8
WR9
WR10
WR11
WR12
WR13
WR14
WR15
Transmit/Receive buffer status, and External status
Special Receive Condition status, residue codes, error conditions
Modified (Channel B only) interrupt vector and Unmodified interrupt
vector (Channel A only)
Interrupt Pending bits (Channel A only)
14-bit frame byte count (LSB)
14-bit frame byte count (MSB), frame status
Receive buffer
Miscellaneous XMTR, RCVR status parameters
Lower byte of baud rate generator time constant
Upper byte of baud rate generator time constant
External/Status interrupt control information
Command Register, (Register Pointers), CRC initialization, resets
for various modes
Interrupt conditions, Wait/DMA request control
Interrupt vector (access through either channel)
Receive/Control parameters, number of bits per character, Rx CRC
enable
Transmit/Receive miscellaneous parameters and codes, clock rate,
number of sync characters, stop bits, parity
Transmit parameters and control, number of Tx bits per character,
Tx CRC enable
Sync character (1st byte) or SDLC address
SYNC character (2nd byte) or SDLC flag
SDLC options; auto flag, RTS, EOM reset, extended read, etc.
Transmit buffer
Master interrupt control and reset (accessed through either
channel), reset bits, control interrupt daisy chain
Miscellaneous transmitter/receiver control bits, NRZI, NRZ, FM
encoding, CRC reset
Clock mode control, source of Rx and Tx clocks
Lower byte of baud rate generator time constant
Upper byte of baud rate generator time constant
Miscellaneous control bits: baud rate generator, Phase-Locked
Loop control, auto echo, local loopback
External/Status interrupt control information-control external
conditions causing interrupts
Table 2–1. Register Set
System Interface