AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 67

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Data Communication Modes Functional Description
SYNC
RTxC
RxD
back SDLC frames by minimizing frame overruns due to CPU latencies in responding to
interrupts. The block diagram of the 10x19-bit FIFO is shown in Figure 4–12.
4.7.1.3.1
This Frame Status FIFO is enabled through WR15 bit D2 but only when the SCC is pro-
grammed in SDLC mode. Since each channel incorporates this FIFO, each can be en-
abled and disabled independently.
Resetting bit D2 of WR15 disables and resets the FIFO. Table 4–2 tabulates the ena-
bling/disabling of channel FIFOs. Note that the FIFO pointer logic is reset when D2 of
WR15 is reset or after a power-on reset.
When the Frame Status FIFO is disabled, the CMOS SCC is completely downward com-
patible with the NMOS SCC, and the status register contents bypass the FIFO and go
directly to the bus interface as shown in Figure 4–12.
The status of the FIFO Enable signal can be obtained by reading bits D2 of RR15 through
their respective channels. If the FIFO is enabled, this bit will be set to ‘1’; otherwise, it will
be set to ‘0’.
4.7.1.3.2
To facilitate the use of these FIFOs, two new registers were added. These registers, RR6
and RR7, are accessible only when bit D2 of WR15 is set to ‘1’, and the SCC is pro-
grammed in SDLC mode.
WR15A(D2)
0
1
1
0
FLAG
FIFO Enabling/Disabling
FIFO Read Operation
LAST–1
WR15B(D2)
Table 4–2. Frame Status FIFO Enabling
0
0
1
1
FLAG
Figure 4–11. Flag Detect Timing
LAST
Operation
Ch.A and Ch.B FIFOs disabled and reset
Ch.A and Ch.B FIFOs enabled but not independent
(resetting D2 or WR15A resets both FIFOs
simultaneously)
Ch.A and Ch.B FIFOs enabled and independent
(resetting D2 in either channel resets only pertinent
FIFO)
Ch.B FIFO enabled only
DATA
0
DATA
1
DATA
AMD
2
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