AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 169

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
7.5
7.5.1
The 68000 has an asynchronous, 16-bit, bidirectional, data bus. Data types supported by
the 68000 are: bit data, integer data of 8-, 16- or 32-bit addresses and binary coded deci-
mal data. It can transfer and accept data in either words or bytes. The DTACK input indi-
cates the completion of a data transfer. When the processor recognizes DTACK during a
read cycle, the data is latched and the bus cycle terminates. When DTACK is recognized
during a write cycle, the bus cycle also terminates. An active transition of DTACK indi-
cates the termination of data transfer on the bus. All control and data lines are sampled
during the 68000’s clock high time. The clock is internally buffered, which results in some
slight differences in the sampling and recognition of various signals. The 68000 mask sets
prior to CC1 and allows DTACK to be recognized as early as S2, and all devices allow
BERR or DTACK to be recognized in S4, S6, etc., which terminates the cycle. If the re-
quired setup time is met during S4, DTACK will be recognized during S5 and S6, and
data will be captured during S6. DTACK signal is internally synchronized to allow for valid
operation in an asynchronous system. If an asynchronous control signal does not meet
the required setup time, it is possible that it may not be recognized during that cycle. Be-
cause of this, synchronous systems must not allow DTACK to precede data by more than
40 to 240 nanoseconds, depending on the speed of the particular processor. I/O is mem-
ory-mapped, i.e., there are no special I/O control signals. Any peripheral is treated as a
memory location.
DMA: This Bus is requested by activating the BR input of the 68000. Bus Arbitration is
started by the BG output going active. The Bus is available when AS becomes inactive.
The requesting device must acknowledge bus mastership by activating the BGACK input
to the CPU.
The 23-bit address (A
Mwords (16 Mbytes) of memory or I/O. It provides the address for bus operation during all
cycles, except the interrupt cycles. During interrupt cycles, address lines A1, A2 and A3
provide information about the level of interrupt being serviced. Instead of A
WORD, there are two separate data strobe lines for the two bytes in a word. A note of
caution here, the 68000 treats the MSB of the lower byte as an even byte, or word ad-
dress. The same goes with processors such as the Z8000. Processors such as the 8086
treat the lower byte as the odd byte.
Interrupt is requested by activating any combination of the interrupt inputs to the 68000
(IPL0 2), indicating the encoded priority level of the interrupt requester (inputs at or be-
low the current processor priority are ignored). The 68000 automatically saves the status
register, switches to supervisor mode, fetches a vector number from the interrupting de-
vice, and displays the interrupt level on the address bus. For interfacing with old 68000
peripherals, the 68000 issues an Enable signal at one-tenth of the processor clock fre-
quency. There are a number of AMD proprietary third generation peripherals that can be
interfaced to the 68000 CPU, to improve system performance. This chapter deals mainly
with the interfacing of the 68000 and the Am8530H.
7–20
INTERFACING TO THE 68000
68000 Overview
1
A
23
) is on an unidirectional, three-state bus and can address 8
SCC Application Notes
0
and BYTE/