AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 132

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
Bit 4: Go Active On Poll
When Loop mode is first selected during SDLC operation, the SCC connects RxD to TxD
with only gate delays in the path. The SCC does not go on-loop and insert the 1-bit delay
between RxD and TxD until this bit has been set and an EOP received. When the SCC is
on-loop, the transmitter is active in SDLC Loop mode and is sending a flag. If this bit is
set at the time the flag is leaving the Transmit Shift register, another flag or data byte (if
the transmit buffer is full) is transmitted. If the Go Active On Poll bit is not set at this time,
the transmitter finishes sending the flag and reverts to the 1-Bit Delay mode. Thus, to
transmit only one response frame, this bit should be reset after the first data byte is sent
to the SCC but before CRC has been transmitted. If the bit is not reset before CRC is
transmitted, extra flags are sent, slowing down response time on the loop. If this bit is re-
set before the first data is written, the SCC completes the transmission of the present flag
and reverts to the 1-Bit Delay mode. After gaining control of the loop, the SCC is not able
to transmit again until a flag and another EOP have been received. Though not strictly
necessary, it is good practice to set this bit only upon receipt of a poll frame to ensure that
the SCC does not go on-loop without the CPU noticing it.
In synchronous modes other than SDLC with the Loop Mode bit set, this bit must be set
before the transmitter can go active in response to a received sync character.
This bit is always ignored in Asynchronous mode and Synchronous modes unless the
Loop Mode bit is set. This bit is reset by a channel or hardware reset.
Bit 3: Mark/ Flag Idle
This bit affects only SDLC operation and is used to control the idle line condition. If this
bit is set to ‘0’, the transmitter sends flags as an idle line. If this bit is set to ‘1’, the trans-
mitter sends continuous ‘1’s after the closing flag of a frame. The idle line condition is se-
lected byte by byte; i.e., either a flag or eight ‘1’s are transmitted. The primary station in
an SDLC loop should be programmed for Mark Idle to create the EOP sequence. Mark
Idle must be deselected at the beginning of a frame before the first data are written to the
SCC, so that an opening flag can be transmitted. This bit is ignored in Loop mode, but the
programmed value takes effect upon exiting the Loop mode. This bit is reset by a channel
or hardware reset.
6–22
D
0
0
1
1
6
Table 6–5. Data Encoding
D
0
1
0
1
5
Encoding
NRZ
NRZI
FM1 (transition = 1)
FM0 (transition = 0)
Register Description