AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 55

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

CHAPTER 4
4.1
The SCC provides two independent full-duplex channels programmable for use in any
common asynchronous or synchronous data communication protocol. This includes:
Asynchronous, Synchronous MONOSYNC (8-bit sync character), Synchronous BISYNC
(16-bit sync character), normal SDLC, and SDLC Loop Mode.
4.2
A communication protocol defines a set of rules for the orderly transfer of information be-
tween two communicating devices. All communication line protocols in the industry today
exchange data in either an asynchronous or synchronous manner. Asynchronous trans-
mission is used in several protocols including the TTY protocol while synchronous trans-
mission is used in protocols which include: IBM BISYNC, Synchronous Data Link Control
(SDLC), High-Level Data Link Control (HDLC), and Advance Data Communication Con-
trol Procedures (ADCCP).
This section provides a brief overview of these protocols; however, if further information is
desired the book titled “Technical Aspects of Data Communications” by John E.
McNamara, published by Digital Press (DEC) 1982, is a good reference.
4.2.1
In Asynchronous transmission, as the name implies, each character is transmitted as an
independent entity; that is, the time between the last bit of one character and the first bit
of another character can be variable.
Since the receiver must be able to detect the beginning of each character transmitted,
this mode requires that at least one bit be added at the start and end of each character
for synchronization purposes.
Synchronization at the receiver is accomplished by sensing the transition of the Start-bit
for each character transmitted. The first data bit of the character is typically sampled one
and one-half bit times after the High-to-Low transition of the Start-bit, and each subse-
quent bit is sampled one bit time thereafter. The sampling of the bit occurs near the cen-
ter of each bit to allow correct data recovery and typically occurs at some multiple of the
data rate. Larger multiples allow a closer approximation to the middle sampling.
Figure 4–1 depicts a typical Asynchronous 11-bit format. Each 8-bit character is preceded
by a Start-bit and followed by a Parity check bit and one Stop-bit. The Start-bit of the next
character can occur anytime after the first character’s Stop-bit. The idle state of the trans-
mission line between characters is always in a mark idle condition (i.e., TxD pulled High).
Asynchronous communication channels are found in most distributed computer systems
for terminal-to-computer comunications. The common “serial port” found on personal
computers is an asynchronous port. It is used to attach external modems and printers,
and to interface the personal computer to a minicomputer for use as a terminal.
Data Communication Modes
Functional Description
Start
D0
X = High or Low
X
D1
X
INTRODUCTION
PROTOCOLS
Asynchronous
D2
X
D3
X
D4
X
D5
X
Figure 4–1. Asynchronous Format
D6
X
D7
X
X
P
Stop
Start
D0
X
D1
X
D2
X
D3
X
D4
X
D5
X
D6
X
D7
X
X
P
Stop
4–3