AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 42

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

I/O Programming Functional Description
The SCC recognizes several Special Conditions during data reception. A Receiver Over-
run, where a character in the Data FIFO is overwritten, is a Special Condition, as is a
Framing Error in Asynchronous mode, or the EOF condition in SDLC mode. In addition, if
bit D2 of WR1 is set to ‘1’, any character with a Parity Error will generate a Special Condi-
tion interrupt.
The correct sequence of events when using this mode is to first select the mode and wait
for the receive character available interrupt. When the interrupt occurs, the processor
should read the character and then enable the DMA to transfer the remaining characters.
A Special Condition interrupt may occur at any time after the first character is received
but is guaranteed to occur after the character having the Special Condition has been read
from the Receive Data FIFO. The status is not lost in this case, however, because the
Data FIFO will be locked by the Special Condition preventing further data from becoming
available in the Receive Data FIFO until the Error Reset command is issued. In the serv-
ice routine the processor should read RR1 to obtain the status and may read the data
again if necessary before unlocking the FIFO by issuing an Error Reset command in
WR0. If the Special Condition detected was EOF, the processor should then issue the
Enable Interrupt on Next Receive Character command to prepare for the next frame. The
first character and Special Condition interrupt are distinguished by the status included in
the interrupt vector. In all other respects they are identical, including sharing the IP and
IUS bits.
In the Am85C30, if the 10x19 Frame Status FIFO is enabled, the 3 byte receive (Rx)
FIFO never locks. However, the DMA is disabled (only on overrun special condition), i.e.
overruns do not lock the Rx FIFO, but do disable DMA. Interrupts are generated and re-
main active until the RESET ERROR COMMAND is issued.
3.6.3
This mode is designed for an interrupt-driven system. In this mode, the SCC will set the
Receiver IP on every received character, whether or not it has a Special Condition. This
includes characters already in the FIFO when this mode is selected. In this mode of op-
eration, the Receiver IP is reset when the character is removed from the FIFO, so if the
processor requires status for any character, this status must be read before the data is
removed from the FIFO.
The Special Conditions are identical to those previously mentioned, and as before, the
only difference between a “receive character available” interrupt and a “Special Condition”
interrupt is the status encoded in the vector. In this mode, a Special Condition does not
lock the Receive Data FIFO so that the service routine must read the status in RR1 be-
fore reading the data. At moderate to high data rates, where the interrupt overhead is sig-
nificant, time can usually be saved by checking for another received character before exit-
ing the service routine. This technique eliminates the Interrupt Acknowledge and the proc-
essor-state-saving time, but care must be exercised because this receive character must
be checked for special receive conditions before it is removed from the SCC.
3.6.4
This mode is designed for use with DMA transfers of the receive characters. In this mode,
only receive characters with Special Conditions will cause the Receive IP to be set. All
other characters are assumed to be transferred via DMA. No special initialization se-
quence is needed in this mode. Usually the DMA is initialized and enabled, and then this
mode is selected in the SCC. A Special Condition interrupt may occur at any time after
this mode is selected, but the logic guarantees that the interrupt will not occur until after
the character with the Special Condition has been read from the SCC. The Special Condi-
tion locks the FIFO so that the status will be valid when read in the interrupt service rou-
tine, and it guarantees that the DMA will not transfer any characters until the Special Con-
dition has been serviced. In the service routine, the processor should read RR1 to obtain
Receive Interrupt on All Receive Characters or
Special Conditions
Receive Interrupt on Special Conditions
AMD
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