AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 34

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

CHAPTER 3
3.1
The SCC can work under one of the following three modes of I/O operations: Polling,
Interrupts, and Block transfer. All three modes involve register manipulation during initiali-
zation and data transfer. Regardless of the communication mode selected, all three I/O
operating modes are available for use and must be programmed in the initialization
routine.
3.2
Polling avoids interrupts and is the simplest mode to implement. In this mode, the soft-
ware must poll the SCC to determine when data are to be written or read from the SCC.
This mode is enabled when the Master Interrupt Enable (MIE) bit in WR9 (D3) and the
Wait/DMA Request Enable bit in WR1 (D7) are both set to ‘0’.
In this mode the software must poll RR0 to determine the status of the Receive Buffer,
Transmit Buffer and External/Status before jumping to the appropriate interrupt routine.
3.3
When the MIE bit in WR9 (D3) is set to ‘1’ interrupts will be enabled and, the SCC as a
microprocessor peripheral, will request an interrupt by asserting the INT pin Low from its
open-drain state only when it needs servicing.
Each channel in the SCC contains three sources of interrupts making a total of six.
These three sources of interrupts are: 1) Receiver, 2) Transmitter, and 3) External/Status
conditions as shown in Figure 3–1. In addition, there are several conditions that may
cause these interrupts. Each interrupt source is enabled under program control, with
Channel A having a higher priority than Channel B and with Receive, Transmit, and Ex-
ternal/Status interrupts prioritized respectively within each channel as shown in
Table 3–1.
I/O Programming Functional
Description
INTRODUCTION
POLLING
INTERRUPT SOURCES
3–3