AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 122

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
Bits 7 and 6: Clock Rate 1 And 0
These bits specify the multiplier between the clock and data rates. In synchronous
modes, the 1X mode is forced internally and these bits are ignored unless External Sync
mode has been selected.
1X Mode (00). The clock rate and data rate are the same. In External Sync mode, this bit
combination specifies that only the SYNC pin can be used to achieve character synchro-
nization.
16X Mode (01). The clock rate is 16 times the data rate. In External Sync mode, this bit
combination specifies that only the SYNC pin can be used to achieve character synchro-
nization.
32X Mode (10). The clock rate is 32 times the data rate. In External Sync mode, this bit
combination specifies that either the SYNC pin or a match with the character stored in
WR7 will signal character synchronization. The sync character can be either six or eight
bits long as specified by the 6-bit/8-bit Sync bit in WR10.
64X Mode (11). The clock rate is 64 times the data rate. With this bit combination in Ex-
ternal Sync mode, both the receiver and transmitter are placed in SDLC mode. The only
variation from normal SDLC operation is that the SYNC pin is used to start or stop the
reception of a frame by forcing the receiver to act as though a flag had been received.
Bits 5 and 4: SYNC Modes 1 And 0
These two bits select the various options for character synchronization. They are ignored
unless synchronous modes are selected in the stop bits field of this register.
Monosync (00). In this mode, the receiver achieves character synchronization by match-
ing the character stored in WR7 with an identical character in the received data stream.
6–12
D
0
0
1
1
7
D
0
1
0
1
6
D
X1 Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode
0
0
1
1
5
Figure 6–5. Write Register 4
D
0
1
0
1
4
D
0
0
1
1
3
8 Bit SYNC Character
16 Bit SYNC Character
SDLC Mode (01111110 Flag)
External SYNC Mode
D
0
1
0
1
2
D
SYNC Modes Enable
1 Stop Bit/Character
1
2 Stop Bits/Character
1
1
/
D
2
Stop Bits/Character
0
Parity Enable
Parity Even/Odd
Register Description