ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 207

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.8.1
Name:
Access Type:
•
0 = No effect.
1 = Enables the SPI to transfer and receive data.
•
0 = No effect.
1 = Disables the SPI.
As soon as SPDIS is set, SPI finishes its transfer.
All pins are set in input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the SPI is disabled.
If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.
•
0 = No effect.
1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.
The SPI is in slave mode after a software reset.
PDC channels are not affected by software reset.
•
0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this
allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD
transfer has completed.
32058J-AVR32-04/11
SPIEN: SPI Enable
SPIDIS: SPI Disable
SWRST: SPI Software Reset
LASTXFER: Last Transfer
SWRST
31
23
15
–
–
–
7
SPI Control Register
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
CR
Write-only
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
26
18
10
–
–
–
–
2
SPIDIS
25
17
–
–
–
9
1
AT32UC3A
LASTXFER
SPIEN
24
16
–
–
8
0
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