ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 278

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.9.3
Name:
Access Type:
Offset:
Reset value:
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception.
When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG
(Receive Sync Data) reception.
• STOP: Receive Stop Selection
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a
new compare 0.
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• START: Receive Start Selection
32058J-AVR32-04/11
0x9-0xF
START
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
31
23
15
–
7
Receive Clock Mode Register
CKG
Continuous, as soon as the receiver is enabled, and immediately after the end of
transfer of the previous data.
Transmit start
Detection of a low level on RX_FRAME_SYNC signal
Detection of a high level on RX_FRAME_SYNC signal
Detection of a falling edge on RX_FRAME_SYNC signal
Detection of a rising edge on RX_FRAME_SYNC signal
Detection of any level change on RX_FRAME_SYNC signal
Detection of any edge on RX_FRAME_SYNC signal
Compare 0
Reserved
Receive Start
30
22
14
RCMR
Read/Write
0x10
0x00000000
–
6
CKI
29
21
13
–
5
STOP
28
20
12
4
PERIOD
STTDLY
CKO
27
19
11
3
26
18
10
2
START
25
17
9
1
AT32UC3A
CKS
24
16
8
0
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