ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 570

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30.8.2.9
Offset:
Register Name:
Access Type:
Reset Value:
• EPENX, X in [0..6]: Endpoint X Enable
Set to enable the endpoint X.
Clear to disable the endpoint X, what forces the endpoint X state to inactive (no answer to USB requests) and resets the
endpoint X registers (UECFGX, UESTAX, UECONX) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR,
EPTYPE).
• EPRSTX, X in [0..6]: Endpoint X Reset
Set by software to reset the endpoint X FIFO prior to any other operation, upon hardware reset or when a USB bus reset
has been received. This resets the endpoint X registers (UECFGX, UESTAX, UECONX) but not the endpoint configuration
(ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence
field (DTSEQ) which can be cleared by setting the RSTDT bit (by setting the RSTDTS bit).
The endpoint configuration remains active and the endpoint is still enabled.
Then, clear by software to complete the reset operation and to start using the FIFO.
Cleared by hardware upon receiving a USB reset.
32058J–AVR32–04/11
31
23
15
–
–
–
7
–
USB Endpoint Enable/Reset Register (UERST)
EPRST6
EPEN6
rwu
30
22
14
rw
–
0
–
6
0
EPRST5
EPEN5
rwu
29
21
13
rw
–
0
–
5
0
0x001C
UERST
Read/Write
0x00000000
EPRST4
EPEN4
rwu
28
20
12
rw
–
0
–
4
0
EPRST3
EPEN3
rwu
27
19
11
rw
–
0
–
3
0
EPRST2
EPEN2
rwu
26
18
10
rw
–
0
–
2
0
EPRST1
EPEN1
rwu
25
17
rw
–
0
9
–
1
0
AT32UC3A
EPRST0
EPEN0
rwu
24
16
rw
–
0
8
–
0
0
570