ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 76

KIT EVAL FOR AT32UC3A0

ATEVK1105

Manufacturer Part Number
ATEVK1105
Description
KIT EVAL FOR AT32UC3A0
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets

Specifications of ATEVK1105

Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A0512
Processor Series
AVR
Data Bus Width
32 bit
Interface Type
USART, TWI, USB, SPI, Ethernet
Operating Supply Voltage
3.3 V
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A0512
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A0
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
13.6.7
Name:
Access Type:
32058J–AVR32–04/11
BODDET: Brown out detection
OSC32RDY: 32 KHz oscillator Ready
OSC1RDY: Oscillator 1 Ready
OSC0RDY: Oscillator 0 Ready
MSKRDY: Mask Ready
CKRDY: Clock Ready
LOCK1: PLL1 locked
LOCK0: PLL0 locked
OSC0RDY
31
23
15
7
-
-
-
Set to 1 when 0 to 1 transition on POSCSR:BODDET bit is detected:
BOD reference value.
Set to 1 when 0 to 1 transition on the POSCSR:OSC32RDY bit is detected:
used as clock source.
Set to 1 when 0 to 1 transition on the POSCSR:OSC1RDY bit is detected:
clock source.
Set to 1 when 0 to 1 transition on the POSCSR:OSC1RDY bit is detected:
clock source.
Set to 1 when 0 to 1 transition on the POSCSR:MSKRDY bit is detected:
(CPU/HSB/PBA/PBB)_MASK registers.
0: The CKSEL register has been written, and the new clock setting is not yet effective.
1: The synchronous clocks have frequencies as indicated in the CKSEL register.
Note: Writing ICR:CKRDY to 1 has no effect.
Set to 1 when 0 to 1 transition on the POSCSR:LOCK1 bit is detected:
source.
Set to 1 when 0 to 1 transition on the POSCSR:LOCK0 bit is detected:
source.
Interrupt Enable/Disable/Mask/Status/Clear
MSKRDY
30
22
14
6
IER/IDR/IMR/ISR/ICR
IER/IDR/ICR: Write-only
IMR/ISR: Read-only
-
-
-
CKRDY
29
21
13
5
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
-
BOD has detected that power supply is going below
PLL 1 is locked and ready to be selected as clock
PLL 0 is locked and ready to be selected as clock
Clocks are now masked according to the
Oscillator 1 is stable and ready to be used as
Oscillator 1 is stable and ready to be used as
The 32 KHz oscillator is stable and ready to be
26
18
10
2
-
-
-
-
OSC32RDY
LOCK1
25
17
9
1
-
-
AT32UC3A
OSC1RDY
BODDET
LOCK0
24
16
8
0
-
76

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