ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 220

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24. Two-Wire Interface (TWI)
24.1
24.2
32058J-AVR32-04/11
Features
Overview
2.1.1.0
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Note:
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made
up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial
EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD
Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master
or a slave with sequential or single-byte access. Multiple master capability is supported. Arbitra-
tion of the bus is performed internally and puts the TWI in slave mode automatically if the bus
arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of
core clock frequencies.
Below,
a full I
Table 24-1.
Note:
I2C Standard
Standard Mode Speed (100 KHz)
Fast Mode Speed (400 KHz)
7 or 10 bits Slave Addressing
START BYTE
Repeated Start (Sr) Condition
ACK and NACK Management
Slope control and input filtering (Fast mode)
Clock stretching
Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices
One, Two or Three Bytes for Slave Address
Sequential Read-write Operations
Master, Multi-master and Slave Mode Operation
Bit Rate: Up to 400 Kbits
General Call Supported in Slave mode
Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in
Master Mode Only
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
2
C compatible device.
Table 24-1
1. See
1. START + b000000001 + Ack + Sr
(1)
Atmel TWI compatibility with I
Table 24-1
lists the compatibility level of the Atmel Two-wire Interface in Master Mode and
below for details on compatibility with I²C Standard.
2
C Standard
Atmel TWI
Supported
Supported
Supported
Not Supported
Supported
Supported
Not Supported
Supported
AT32UC3A
(1)
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