ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 243

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.13.6.2
Figure 24-27. Clock Synchronization in Write Mode
Notes:
32058J-AVR32-04/11
TWI_RHR
TXCOMP
SVREAD
SCLWS
RXRDY
SVACC
TWCK
1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mecha-
TWD
SADR.
nism is finished.
Clock Synchronization in Write Mode
S
SADR
As soon as a START is detected
The clock is tied low if the shift register and the RHR is full. If a STOP or REPEATED_START
condition was not detected, it is tied low until RHR is read.
Figure 24-27 on page 243
W
A
DATA0
CLOCK is tied low by the TWI as long as RHR is full
A
describes the clock synchronization in Read mode.
DATA1
DATA0 is not read in the RHR
SCL is stretched on the last bit of DATA1
Rd DATA0
A
Rd DATA1
DATA1
DATA2
NA
Rd DATA2
DATA2
AT32UC3A
S
ADR
243