ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 518

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 30-19. Abort Algorithm
30.7.2.13
30.7.2.13.1 Overview
32058J–AVR32–04/11
Management of OUT Endpoints
OUT packets are sent by the host. All the data can be read by the firmware which acknowledges
or not the bank when it is empty.
The endpoint must be configured first.
The RXOUTI bit is set by hardware at the same time as FIFOCON when the current bank is full.
This triggers an EPXINT interrupt if RXOUTE = 1.
RXOUTI shall be cleared by software (by setting the RXOUTIC bit) to acknowledge the interrupt,
what has no effect on the endpoint FIFO.
The firmware then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT
endpoint is composed of multiple banks, this also switches to the next bank. The RXOUTI and
FIFOCON bits are updated by hardware in accordance with the status of the next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWALL bit is set by hardware when the current bank is not empty, i.e. the software can read
further data from the FIFO.
EPRSTX = 1
TXINEC = 1
Abort Done
NBUSYBK
Endpoint
== 0?
Abort
Yes
No
Yes
KILLBKS = 1
KILLBK
== 1?
No
Disable the TXINI interrupt.
Abort is based on the fact
that no bank is busy, i.e. that
nothing has to be sent.
Kill the last written bank.
Wait for the end of the
procedure.
AT32UC3A
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