ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 49

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.10 GPIO
12.11 Peripheral overview
12.11.1
12.11.2
12.11.3
32058J–AVR32–04/11
External Bus Interface
Static Memory Controller
SDRAM Controller
The GPIO open drain feature (GPIO ODMER register (Open Drain Mode Enable Register)) is
not available for this device.
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Optimized for Application Memory Space support
Integrates Two External Memory Controllers:
Optimized External Bus:
4 SRAM Chip Selects, 1SDRAM Chip Select:
4 Chip Selects Available
64-Mbyte Address Space per Chip Select
8-, 16-bit Data Bus
Word, Halfword, Byte Transfers
Byte Write or Byte Select Lines
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
Compliant with LCD Module
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
Numerous Configurations Supported
Programming Facilities
Energy-saving Capabilities
– Static Memory Controller
– SDRAM Controller
– 16-bit Data Bus
– 24-bit Address Bus, Up to 16-Mbytes Addressable
– Optimized pin multiplexing to reduce latencies on External Memories
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with Two or Four Internal Banks
– SDRAM with 16-bit Data Path
– Word, Half-word, Byte Access
– Automatic Page Break When Memory Boundary Has Been Reached
– Multibank Ping-pong Access
– Timing Parameters Specified by Software
– Automatic Refresh Operation, Refresh Rate is Programmable
– Self-refresh, Power-down and Deep Power Modes Supported
AT32UC3A
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