ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 381

KIT EVAL FOR AT32UC3A0

ATEVK1105

Manufacturer Part Number
ATEVK1105
Description
KIT EVAL FOR AT32UC3A0
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets

Specifications of ATEVK1105

Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A0512
Processor Series
AVR
Data Bus Width
32 bit
Interface Type
USART, TWI, USB, SPI, Ethernet
Operating Supply Voltage
3.3 V
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A0512
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A0
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
27.6.4.6
32058J–AVR32–04/11
– Write is Controlled by NCS (WRITE_MODE = 0)
Coding Timing Parameters
Figure 27-15. WRITE_MODE = 1. The write operation is controlled by NWE
Figure 27-16
put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are
turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of
the programmed waveform on NWE.
Figure 27-16. WRITE_MODE = 0. The write operation is controlled by NCS
All timing parameters are defined for one chip select and are grouped together in one REGIS-
TER according to their type.
NWR0, NWR1
NWR0, NWR1
NBS0, NBS1,
NBS0, NBS1,
A0, A1
A0, A1
CLK_SMC
CLK_SMC
NWE,
D[15:0]
NWE,
D[15:0]
A[25:2]
A[25:2]
NCS
NCS
shows the waveforms of a write operation with WRITE_MODE set to 0. The data is
AT32UC3A
381

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