ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 499
![KIT EVAL FOR AT32UC3A0](/photos/9/20/92036/atevk1105_sml.jpg)
ATEVK1105
Manufacturer Part Number
ATEVK1105
Description
KIT EVAL FOR AT32UC3A0
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1105.pdf
(28 pages)
Specifications of ATEVK1105
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A0512
Processor Series
AVR
Data Bus Width
32 bit
Interface Type
USART, TWI, USB, SPI, Ethernet
Operating Supply Voltage
3.3 V
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A0512
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A0
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 499 of 826
- Download datasheet (20Mb)
30.3
Figure 30-1. Block Diagram
32058J–AVR32–04/11
Block Diagram
Controller
Manager
Interrupt
Power
HSB
PB
USB GCLK @ 48 MHz
USB
The USB controller provides a hardware device to interface a USB link to a data flow stored in a
dual-port RAM (DPRAM).
The USB controller requires a 48 MHz ± 0.25% reference clock, which is the USB generic clock
generated from one of the power manager oscillators, optionally through one of the power man-
ager PLLs.
The 48 MHz clock is used to generate a 12 MHz full-speed (or 1.5 MHz low-speed) bit clock from
the received USB differential data and to transmit data according to full- or low-speed USB
device tolerance. Clock recovery is achieved by a digital phase-locked loop (a DPLL, not repre-
sented), which complies with the USB jitter specifications.
HSB MUX
Master
Slave
HSB0
HSB1
Slave Interface
User Interface
Local
DMA
HSB
USB Interrupts
32 bits
System Clock
Domain
Allocation
USB 2.0
DPRAM
Core
PEP
USB Clock
Domain
Controller
GPIO
AT32UC3A
VBUS
D-
D+
USB_ID
USB_VBOF
499
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