ATEVK1105 Atmel, ATEVK1105 Datasheet - Page 6

• Manufacturer Part Number: ATEVK1105
• Description: KIT EVAL FOR AT32UC3A0
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1105

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A0512
• Processor Series: AVR
• Data Bus Width: 32 bit
• Interface Type: USART, TWI, USB, SPI, Ethernet
• Operating Supply Voltage: 3.3 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A0512
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.1
4.1.1
4.1.2
4.1.3
4.1.4
32058J–AVR32–04/11
Processor and architecture
AVR32 UC CPU
Debug and Test system
Peripheral DMA Controller
Bus system
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32-bit load/store AVR32A RISC architecture.
3 stage pipeline allows one instruction per clock cycle for most instructions.
MPU allows for operating systems with memory protection.
IEEE1149.1 compliant JTAG and boundary scan
Direct memory access and programming capabilities through JTAG interface
Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
Auxiliary port for high-speed trace information
Hardware support for 6 Program and 2 data breakpoints
Unlimited number of software breakpoints supported
Advanced Program, Data, Ownership, and Watchpoint trace supported
Transfers from/to peripheral to/from any memory space without intervention of the processor.
Next Pointer Support, forbids strong real-time constraints on buffer management.
Fifteen channels
High Speed Bus (HSB) matrix with 6 Masters and 6 Slaves handled
– 15 general-purpose 32-bit registers.
– 32-bit Stack Pointer, Program Counter and Link Register reside in register file.
– Fully orthogonal instruction set.
– Privileged and unprivileged modes enabling efficient and secure Operating Systems.
– Innovative instruction set together with variable instruction length ensuring industry leading
– DSP extention with saturating arithmetic, and a wide variety of multiply instructions.
– Byte, half-word, word and double word memory access.
– Multiple interrupt priority levels.
– Low-cost NanoTrace supported.
– Two for each USART
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for each ADC
– Two for each TWI Interface
– Handles Requests from the CPU Data Fetch, CPU Instruction Fetch, PDCA, USBB, Ethernet
– Round-Robin Arbitration (three modes supported: no default master, last
– Burst Breaking with Slot Cycle Limit
– One Address Decoder Provided per Master
code density.
Controller, CPU SAB, and to internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus
B, EBI.
master, fixed default master)
AT32UC3A
accessed default
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